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| </pre><div class="example-wrap"><pre class="rust "> |
| <span class="comment">// # References</span> |
| <span class="comment">//</span> |
| <span class="comment">// - Section 7.4 "Hints" of ACLE</span> |
| <span class="comment">// - Section 7.7 "NOP" of ACLE</span> |
| |
| <span class="doccomment">/// Generates a WFI (wait for interrupt) hint instruction, or nothing.</span> |
| <span class="doccomment">///</span> |
| <span class="doccomment">/// The WFI instruction allows (but does not require) the processor to enter a</span> |
| <span class="doccomment">/// low-power state until one of a number of asynchronous events occurs.</span> |
| <span class="comment">// Section 10.1 of ACLE says that the supported arches are: 8, 6K, 6-M</span> |
| <span class="comment">// LLVM says "instruction requires: armv6k"</span> |
| <span class="attribute">#[<span class="ident">cfg</span>(<span class="ident">any</span>(<span class="ident">target_feature</span> <span class="op">=</span> <span class="string">"v6"</span>, <span class="ident">target_arch</span> <span class="op">=</span> <span class="string">"aarch64"</span>))]</span> |
| <span class="attribute">#[<span class="ident">inline</span>(<span class="ident">always</span>)]</span> |
| <span class="kw">pub</span> <span class="kw">unsafe</span> <span class="kw">fn</span> <span class="ident">__wfi</span>() { |
| <span class="ident">hint</span>(<span class="ident">HINT_WFI</span>); |
| } |
| |
| <span class="doccomment">/// Generates a WFE (wait for event) hint instruction, or nothing.</span> |
| <span class="doccomment">///</span> |
| <span class="doccomment">/// The WFE instruction allows (but does not require) the processor to enter a</span> |
| <span class="doccomment">/// low-power state until some event occurs such as a SEV being issued by</span> |
| <span class="doccomment">/// another processor.</span> |
| <span class="comment">// Section 10.1 of ACLE says that the supported arches are: 8, 6K, 6-M</span> |
| <span class="comment">// LLVM says "instruction requires: armv6k"</span> |
| <span class="attribute">#[<span class="ident">cfg</span>(<span class="ident">any</span>(<span class="ident">target_feature</span> <span class="op">=</span> <span class="string">"v6"</span>, <span class="ident">target_arch</span> <span class="op">=</span> <span class="string">"aarch64"</span>))]</span> |
| <span class="attribute">#[<span class="ident">inline</span>(<span class="ident">always</span>)]</span> |
| <span class="kw">pub</span> <span class="kw">unsafe</span> <span class="kw">fn</span> <span class="ident">__wfe</span>() { |
| <span class="ident">hint</span>(<span class="ident">HINT_WFE</span>); |
| } |
| |
| <span class="doccomment">/// Generates a SEV (send a global event) hint instruction.</span> |
| <span class="doccomment">///</span> |
| <span class="doccomment">/// This causes an event to be signaled to all processors in a multiprocessor</span> |
| <span class="doccomment">/// system. It is a NOP on a uniprocessor system.</span> |
| <span class="comment">// Section 10.1 of ACLE says that the supported arches are: 8, 6K, 6-M, 7-M</span> |
| <span class="comment">// LLVM says "instruction requires: armv6k"</span> |
| <span class="attribute">#[<span class="ident">cfg</span>(<span class="ident">any</span>(<span class="ident">target_feature</span> <span class="op">=</span> <span class="string">"v6"</span>, <span class="ident">target_arch</span> <span class="op">=</span> <span class="string">"aarch64"</span>))]</span> |
| <span class="attribute">#[<span class="ident">inline</span>(<span class="ident">always</span>)]</span> |
| <span class="kw">pub</span> <span class="kw">unsafe</span> <span class="kw">fn</span> <span class="ident">__sev</span>() { |
| <span class="ident">hint</span>(<span class="ident">HINT_SEV</span>); |
| } |
| |
| <span class="doccomment">/// Generates a send a local event hint instruction.</span> |
| <span class="doccomment">///</span> |
| <span class="doccomment">/// This causes an event to be signaled to only the processor executing this</span> |
| <span class="doccomment">/// instruction. In a multiprocessor system, it is not required to affect the</span> |
| <span class="doccomment">/// other processors.</span> |
| <span class="comment">// LLVM says "instruction requires: armv8"</span> |
| <span class="attribute">#[<span class="ident">cfg</span>(<span class="ident">any</span>( |
| <span class="ident">target_feature</span> <span class="op">=</span> <span class="string">"v8"</span>, <span class="comment">// 32-bit ARMv8</span> |
| <span class="ident">target_arch</span> <span class="op">=</span> <span class="string">"aarch64"</span>, <span class="comment">// AArch64</span> |
| ))]</span> |
| <span class="attribute">#[<span class="ident">inline</span>(<span class="ident">always</span>)]</span> |
| <span class="kw">pub</span> <span class="kw">unsafe</span> <span class="kw">fn</span> <span class="ident">__sevl</span>() { |
| <span class="ident">hint</span>(<span class="ident">HINT_SEVL</span>); |
| } |
| |
| <span class="doccomment">/// Generates a YIELD hint instruction.</span> |
| <span class="doccomment">///</span> |
| <span class="doccomment">/// This enables multithreading software to indicate to the hardware that it is</span> |
| <span class="doccomment">/// performing a task, for example a spin-lock, that could be swapped out to</span> |
| <span class="doccomment">/// improve overall system performance.</span> |
| <span class="comment">// Section 10.1 of ACLE says that the supported arches are: 8, 6K, 6-M</span> |
| <span class="comment">// LLVM says "instruction requires: armv6k"</span> |
| <span class="attribute">#[<span class="ident">cfg</span>(<span class="ident">any</span>(<span class="ident">target_feature</span> <span class="op">=</span> <span class="string">"v6"</span>, <span class="ident">target_arch</span> <span class="op">=</span> <span class="string">"aarch64"</span>))]</span> |
| <span class="attribute">#[<span class="ident">inline</span>(<span class="ident">always</span>)]</span> |
| <span class="kw">pub</span> <span class="kw">unsafe</span> <span class="kw">fn</span> <span class="ident">__yield</span>() { |
| <span class="ident">hint</span>(<span class="ident">HINT_YIELD</span>); |
| } |
| |
| <span class="doccomment">/// Generates a DBG instruction.</span> |
| <span class="doccomment">///</span> |
| <span class="doccomment">/// This provides a hint to debugging and related systems. The argument must be</span> |
| <span class="doccomment">/// a constant integer from 0 to 15 inclusive. See implementation documentation</span> |
| <span class="doccomment">/// for the effect (if any) of this instruction and the meaning of the</span> |
| <span class="doccomment">/// argument. This is available only when compliling for AArch32.</span> |
| <span class="comment">// Section 10.1 of ACLE says that the supported arches are: 7, 7-M</span> |
| <span class="comment">// "The DBG hint instruction is added in ARMv7. It is UNDEFINED in the ARMv6 base architecture, and</span> |
| <span class="comment">// executes as a NOP instruction in ARMv6K and ARMv6T2." - ARM Architecture Reference Manual ARMv7-A</span> |
| <span class="comment">// and ARMv7-R edition (ARM DDI 0406C.c) sections D12.4.1 "ARM instruction set support" and D12.4.2</span> |
| <span class="comment">// "Thumb instruction set support"</span> |
| <span class="attribute">#[<span class="ident">cfg</span>(<span class="ident">target_feature</span> <span class="op">=</span> <span class="string">"v7"</span>)]</span> |
| <span class="attribute">#[<span class="ident">inline</span>(<span class="ident">always</span>)]</span> |
| <span class="attribute">#[<span class="ident">rustc_args_required_const</span>(<span class="number">0</span>)]</span> |
| <span class="kw">pub</span> <span class="kw">unsafe</span> <span class="kw">fn</span> <span class="ident">__dbg</span>(<span class="ident">imm4</span>: <span class="ident">u32</span>) { |
| <span class="macro">macro_rules</span><span class="macro">!</span> <span class="ident">call</span> { |
| (<span class="macro-nonterminal">$</span><span class="macro-nonterminal">imm4</span>:<span class="ident">expr</span>) <span class="op">=></span> { |
| <span class="macro">asm</span><span class="macro">!</span>(<span class="macro">concat</span><span class="macro">!</span>(<span class="string">"DBG "</span>, <span class="macro">stringify</span><span class="macro">!</span>(<span class="macro-nonterminal">$</span><span class="macro-nonterminal">imm4</span>)) : : : : <span class="string">"volatile"</span>) |
| } |
| } |
| |
| <span class="kw">match</span> <span class="ident">imm4</span> <span class="op">&</span> <span class="number">0b1111</span> { |
| <span class="number">0</span> <span class="op">=></span> <span class="macro">call</span><span class="macro">!</span>(<span class="number">0</span>), |
| <span class="number">1</span> <span class="op">=></span> <span class="macro">call</span><span class="macro">!</span>(<span class="number">1</span>), |
| <span class="number">2</span> <span class="op">=></span> <span class="macro">call</span><span class="macro">!</span>(<span class="number">2</span>), |
| <span class="number">3</span> <span class="op">=></span> <span class="macro">call</span><span class="macro">!</span>(<span class="number">3</span>), |
| <span class="number">4</span> <span class="op">=></span> <span class="macro">call</span><span class="macro">!</span>(<span class="number">4</span>), |
| <span class="number">5</span> <span class="op">=></span> <span class="macro">call</span><span class="macro">!</span>(<span class="number">5</span>), |
| <span class="number">6</span> <span class="op">=></span> <span class="macro">call</span><span class="macro">!</span>(<span class="number">6</span>), |
| <span class="number">7</span> <span class="op">=></span> <span class="macro">call</span><span class="macro">!</span>(<span class="number">7</span>), |
| <span class="number">8</span> <span class="op">=></span> <span class="macro">call</span><span class="macro">!</span>(<span class="number">8</span>), |
| <span class="number">9</span> <span class="op">=></span> <span class="macro">call</span><span class="macro">!</span>(<span class="number">9</span>), |
| <span class="number">10</span> <span class="op">=></span> <span class="macro">call</span><span class="macro">!</span>(<span class="number">10</span>), |
| <span class="number">11</span> <span class="op">=></span> <span class="macro">call</span><span class="macro">!</span>(<span class="number">11</span>), |
| <span class="number">12</span> <span class="op">=></span> <span class="macro">call</span><span class="macro">!</span>(<span class="number">12</span>), |
| <span class="number">13</span> <span class="op">=></span> <span class="macro">call</span><span class="macro">!</span>(<span class="number">13</span>), |
| <span class="number">14</span> <span class="op">=></span> <span class="macro">call</span><span class="macro">!</span>(<span class="number">14</span>), |
| <span class="kw">_</span> <span class="op">=></span> <span class="macro">call</span><span class="macro">!</span>(<span class="number">15</span>), |
| } |
| } |
| |
| <span class="doccomment">/// Generates an unspecified no-op instruction.</span> |
| <span class="doccomment">///</span> |
| <span class="doccomment">/// Note that not all architectures provide a distinguished NOP instruction. On</span> |
| <span class="doccomment">/// those that do, it is unspecified whether this intrinsic generates it or</span> |
| <span class="doccomment">/// another instruction. It is not guaranteed that inserting this instruction</span> |
| <span class="doccomment">/// will increase execution time.</span> |
| <span class="attribute">#[<span class="ident">inline</span>(<span class="ident">always</span>)]</span> |
| <span class="kw">pub</span> <span class="kw">unsafe</span> <span class="kw">fn</span> <span class="ident">__nop</span>() { |
| <span class="macro">asm</span><span class="macro">!</span>(<span class="string">"NOP"</span> : : : : <span class="string">"volatile"</span>) |
| } |
| |
| <span class="kw">extern</span> <span class="string">"C"</span> { |
| <span class="attribute">#[<span class="ident">cfg_attr</span>(<span class="ident">target_arch</span> <span class="op">=</span> <span class="string">"aarch64"</span>, <span class="ident">link_name</span> <span class="op">=</span> <span class="string">"llvm.aarch64.hint"</span>)]</span> |
| <span class="attribute">#[<span class="ident">cfg_attr</span>(<span class="ident">target_arch</span> <span class="op">=</span> <span class="string">"arm"</span>, <span class="ident">link_name</span> <span class="op">=</span> <span class="string">"llvm.arm.hint"</span>)]</span> |
| <span class="kw">fn</span> <span class="ident">hint</span>(<span class="kw">_</span>: <span class="ident">i32</span>); |
| } |
| |
| <span class="comment">// from LLVM 7.0.1's lib/Target/ARM/{ARMInstrThumb,ARMInstrInfo,ARMInstrThumb2}.td</span> |
| <span class="kw">const</span> <span class="ident">HINT_NOP</span>: <span class="ident">i32</span> <span class="op">=</span> <span class="number">0</span>; |
| <span class="kw">const</span> <span class="ident">HINT_YIELD</span>: <span class="ident">i32</span> <span class="op">=</span> <span class="number">1</span>; |
| <span class="kw">const</span> <span class="ident">HINT_WFE</span>: <span class="ident">i32</span> <span class="op">=</span> <span class="number">2</span>; |
| <span class="kw">const</span> <span class="ident">HINT_WFI</span>: <span class="ident">i32</span> <span class="op">=</span> <span class="number">3</span>; |
| <span class="kw">const</span> <span class="ident">HINT_SEV</span>: <span class="ident">i32</span> <span class="op">=</span> <span class="number">4</span>; |
| <span class="kw">const</span> <span class="ident">HINT_SEVL</span>: <span class="ident">i32</span> <span class="op">=</span> <span class="number">5</span>; |
| </pre></div> |
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