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</pre><div class="example-wrap"><pre class="rust ">
<span class="doccomment">//! ARM C Language Extensions (ACLE)</span>
<span class="doccomment">//!</span>
<span class="doccomment">//! # Developer notes</span>
<span class="doccomment">//!</span>
<span class="doccomment">//! Below is a list of built-in targets that are representative of the different ARM</span>
<span class="doccomment">//! architectures; the list includes the `target_feature`s they possess.</span>
<span class="doccomment">//!</span>
<span class="doccomment">//! - `armv4t-unknown-linux-gnueabi` - **ARMv4** - `+v4t`</span>
<span class="doccomment">//! - `armv5te-unknown-linux-gnueabi` - **ARMv5TE** - `+v4t +v5te`</span>
<span class="doccomment">//! - `arm-unknown-linux-gnueabi` - **ARMv6** - `+v4t +v5te +v6`</span>
<span class="doccomment">//! - `thumbv6m-none-eabi` - **ARMv6-M** - `+v4t +v5te +v6 +thumb-mode +mclass`</span>
<span class="doccomment">//! - `armv7-unknown-linux-gnueabihf` - **ARMv7-A** - `+v4t +v5te +v6 +v6k +v6t2 +v7 +dsp +thumb2 +aclass`</span>
<span class="doccomment">//! - `armv7r-none-eabi` - **ARMv7-R** - `+v4t +v5te +v6 +v6k +v6t2 +v7 +dsp +thumb2 +rclass`</span>
<span class="doccomment">//! - `thumbv7m-none-eabi` - **ARMv7-M** - `+v4t +v5te +v6 +v6k +v6t2 +v7 +thumb2 +thumb-mode +mclass`</span>
<span class="doccomment">//! - `thumbv7em-none-eabi` - **ARMv7E-M** - `+v4t +v5te +v6 +v6k +v6t2 +v7 +dsp +thumb2 +thumb-mode +mclass`</span>
<span class="doccomment">//! - `thumbv8m.main-none-eabi` - **ARMv8-M** - `+v4t +v5te +v6 +v6k +v6t2 +v7 +thumb2 +thumb-mode +mclass`</span>
<span class="doccomment">//! - `armv8r-none-eabi` - **ARMv8-R** - `+v4t +v5te +v6 +v6k +v6t2 +v7 +v8 +thumb2 +rclass`</span>
<span class="doccomment">//! - `aarch64-unknown-linux-gnu` - **ARMv8-A (AArch64)** - `+fp +neon`</span>
<span class="doccomment">//!</span>
<span class="doccomment">//! Section 10.1 of ACLE says:</span>
<span class="doccomment">//!</span>
<span class="doccomment">//! - &quot;In the sequence of Arm architectures { v5, v5TE, v6, v6T2, v7 } each architecture includes</span>
<span class="doccomment">//! its predecessor instruction set.&quot;</span>
<span class="doccomment">//!</span>
<span class="doccomment">//! - &quot;In the sequence of Thumb-only architectures { v6-M, v7-M, v7E-M } each architecture includes</span>
<span class="doccomment">//! its predecessor instruction set.&quot;</span>
<span class="doccomment">//!</span>
<span class="doccomment">//! From that info and from looking at how LLVM features work (using custom targets) we can identify</span>
<span class="doccomment">//! features that are subsets of others:</span>
<span class="doccomment">//!</span>
<span class="doccomment">//! Legend: `a &lt; b` reads as &quot;`a` is a subset of `b`&quot;; this means that if `b` is enabled then `a` is</span>
<span class="doccomment">//! enabled as well.</span>
<span class="doccomment">//!</span>
<span class="doccomment">//! - `v4t &lt; v5te &lt; v6 &lt; v6k &lt; v6t2 &lt; v7 &lt; v8`</span>
<span class="doccomment">//! - `v6 &lt; v8m &lt; v6t2`</span>
<span class="doccomment">//! - `v7 &lt; v8m.main`</span>
<span class="doccomment">//!</span>
<span class="doccomment">//! *NOTE*: Section 5.4.7 of ACLE says:</span>
<span class="doccomment">//!</span>
<span class="doccomment">//! - &quot;__ARM_FEATURE_DSP is defined to 1 if the DSP (v5E) instructions are supported and the</span>
<span class="doccomment">//! intrinsics defined in Saturating intrinsics are available.&quot;</span>
<span class="doccomment">//!</span>
<span class="doccomment">//! This does *not* match how LLVM uses the &#39;+dsp&#39; feature; this feature is not set for v5te</span>
<span class="doccomment">//! targets so we have to work around this difference.</span>
<span class="doccomment">//!</span>
<span class="doccomment">//! # References</span>
<span class="doccomment">//!</span>
<span class="doccomment">//! - [ACLE Q2 2018](https://developer.arm.com/docs/101028/latest)</span>
<span class="comment">// 8, 7 and 6-M are supported via dedicated instructions like DMB. All other arches are supported</span>
<span class="comment">// via CP15 instructions. See Section 10.1 of ACLE</span>
<span class="kw">mod</span> <span class="ident">barrier</span>;
<span class="kw">pub</span> <span class="kw">use</span> <span class="self">self</span>::<span class="ident">barrier</span>::<span class="kw-2">*</span>;
<span class="kw">mod</span> <span class="ident">hints</span>;
<span class="kw">pub</span> <span class="kw">use</span> <span class="self">self</span>::<span class="ident">hints</span>::<span class="kw-2">*</span>;
<span class="kw">mod</span> <span class="ident">registers</span>;
<span class="kw">pub</span> <span class="kw">use</span> <span class="self">self</span>::<span class="ident">registers</span>::<span class="kw-2">*</span>;
<span class="kw">mod</span> <span class="ident">ex</span>;
<span class="kw">pub</span> <span class="kw">use</span> <span class="self">self</span>::<span class="ident">ex</span>::<span class="kw-2">*</span>;
<span class="comment">// Supported arches: 5TE, 7E-M. See Section 10.1 of ACLE (e.g. QADD)</span>
<span class="comment">// We also include the A profile even though DSP is deprecated on that profile as of ACLE 2.0 (see</span>
<span class="comment">// section 5.4.7)</span>
<span class="comment">// Here we workaround the difference between LLVM&#39;s +dsp and ACLE&#39;s __ARM_FEATURE_DSP by gating on</span>
<span class="comment">// &#39;+v5te&#39; rather than on &#39;+dsp&#39;</span>
<span class="attribute">#[<span class="ident">cfg</span>(<span class="ident">all</span>(
<span class="ident">not</span>(<span class="ident">target_arch</span> <span class="op">=</span> <span class="string">&quot;aarch64&quot;</span>),
<span class="ident">any</span>(
<span class="comment">// &gt;= v5TE but excludes v7-M</span>
<span class="ident">all</span>(<span class="ident">target_feature</span> <span class="op">=</span> <span class="string">&quot;v5te&quot;</span>, <span class="ident">not</span>(<span class="ident">target_feature</span> <span class="op">=</span> <span class="string">&quot;mclass&quot;</span>)),
<span class="comment">// v7E-M</span>
<span class="ident">all</span>(<span class="ident">target_feature</span> <span class="op">=</span> <span class="string">&quot;mclass&quot;</span>, <span class="ident">target_feature</span> <span class="op">=</span> <span class="string">&quot;dsp&quot;</span>),
)
))]</span>
<span class="kw">mod</span> <span class="ident">dsp</span>;
<span class="attribute">#[<span class="ident">cfg</span>(<span class="ident">all</span>(
<span class="ident">not</span>(<span class="ident">target_arch</span> <span class="op">=</span> <span class="string">&quot;aarch64&quot;</span>),
<span class="ident">any</span>(
<span class="ident">all</span>(<span class="ident">target_feature</span> <span class="op">=</span> <span class="string">&quot;v5te&quot;</span>, <span class="ident">not</span>(<span class="ident">target_feature</span> <span class="op">=</span> <span class="string">&quot;mclass&quot;</span>)),
<span class="ident">all</span>(<span class="ident">target_feature</span> <span class="op">=</span> <span class="string">&quot;mclass&quot;</span>, <span class="ident">target_feature</span> <span class="op">=</span> <span class="string">&quot;dsp&quot;</span>),
)
))]</span>
<span class="kw">pub</span> <span class="kw">use</span> <span class="self">self</span>::<span class="ident">dsp</span>::<span class="kw-2">*</span>;
<span class="comment">// Supported arches: 6, 7-M. See Section 10.1 of ACLE (e.g. SSAT)</span>
<span class="attribute">#[<span class="ident">cfg</span>(<span class="ident">all</span>(<span class="ident">not</span>(<span class="ident">target_arch</span> <span class="op">=</span> <span class="string">&quot;aarch64&quot;</span>), <span class="ident">target_feature</span> <span class="op">=</span> <span class="string">&quot;v6&quot;</span>,))]</span>
<span class="kw">mod</span> <span class="ident">sat</span>;
<span class="attribute">#[<span class="ident">cfg</span>(<span class="ident">all</span>(<span class="ident">not</span>(<span class="ident">target_arch</span> <span class="op">=</span> <span class="string">&quot;aarch64&quot;</span>), <span class="ident">target_feature</span> <span class="op">=</span> <span class="string">&quot;v6&quot;</span>,))]</span>
<span class="kw">pub</span> <span class="kw">use</span> <span class="self">self</span>::<span class="ident">sat</span>::<span class="kw-2">*</span>;
<span class="comment">// Deprecated in ACLE 2.0 for the A profile but fully supported on the M and R profiles, says</span>
<span class="comment">// Section 5.4.9 of ACLE. We&#39;ll expose these for the A profile even if deprecated</span>
<span class="attribute">#[<span class="ident">cfg</span>(<span class="ident">all</span>(
<span class="ident">not</span>(<span class="ident">target_arch</span> <span class="op">=</span> <span class="string">&quot;aarch64&quot;</span>),
<span class="ident">any</span>(
<span class="comment">// v7-A, v7-R</span>
<span class="ident">all</span>(<span class="ident">target_feature</span> <span class="op">=</span> <span class="string">&quot;v6&quot;</span>, <span class="ident">not</span>(<span class="ident">target_feature</span> <span class="op">=</span> <span class="string">&quot;mclass&quot;</span>)),
<span class="comment">// v7E-M</span>
<span class="ident">all</span>(<span class="ident">target_feature</span> <span class="op">=</span> <span class="string">&quot;mclass&quot;</span>, <span class="ident">target_feature</span> <span class="op">=</span> <span class="string">&quot;dsp&quot;</span>)
)
))]</span>
<span class="kw">mod</span> <span class="ident">simd32</span>;
<span class="attribute">#[<span class="ident">cfg</span>(<span class="ident">all</span>(
<span class="ident">not</span>(<span class="ident">target_arch</span> <span class="op">=</span> <span class="string">&quot;aarch64&quot;</span>),
<span class="ident">any</span>(
<span class="ident">all</span>(<span class="ident">target_feature</span> <span class="op">=</span> <span class="string">&quot;v6&quot;</span>, <span class="ident">not</span>(<span class="ident">target_feature</span> <span class="op">=</span> <span class="string">&quot;mclass&quot;</span>)),
<span class="ident">all</span>(<span class="ident">target_feature</span> <span class="op">=</span> <span class="string">&quot;mclass&quot;</span>, <span class="ident">target_feature</span> <span class="op">=</span> <span class="string">&quot;dsp&quot;</span>)
)
))]</span>
<span class="kw">pub</span> <span class="kw">use</span> <span class="self">self</span>::<span class="ident">simd32</span>::<span class="kw-2">*</span>;
<span class="kw">mod</span> <span class="ident">sealed</span> {
<span class="kw">pub</span> <span class="kw">trait</span> <span class="ident">Dmb</span> {
<span class="kw">unsafe</span> <span class="kw">fn</span> <span class="ident">__dmb</span>(<span class="kw-2">&amp;</span><span class="self">self</span>);
}
<span class="kw">pub</span> <span class="kw">trait</span> <span class="ident">Dsb</span> {
<span class="kw">unsafe</span> <span class="kw">fn</span> <span class="ident">__dsb</span>(<span class="kw-2">&amp;</span><span class="self">self</span>);
}
<span class="kw">pub</span> <span class="kw">trait</span> <span class="ident">Isb</span> {
<span class="kw">unsafe</span> <span class="kw">fn</span> <span class="ident">__isb</span>(<span class="kw-2">&amp;</span><span class="self">self</span>);
}
<span class="kw">pub</span> <span class="kw">trait</span> <span class="ident">Rsr</span> {
<span class="kw">unsafe</span> <span class="kw">fn</span> <span class="ident">__rsr</span>(<span class="kw-2">&amp;</span><span class="self">self</span>) <span class="op">-&gt;</span> <span class="ident">u32</span>;
}
<span class="kw">pub</span> <span class="kw">trait</span> <span class="ident">Rsr64</span> {
<span class="kw">unsafe</span> <span class="kw">fn</span> <span class="ident">__rsr64</span>(<span class="kw-2">&amp;</span><span class="self">self</span>) <span class="op">-&gt;</span> <span class="ident">u64</span>;
}
<span class="kw">pub</span> <span class="kw">trait</span> <span class="ident">Rsrp</span> {
<span class="kw">unsafe</span> <span class="kw">fn</span> <span class="ident">__rsrp</span>(<span class="kw-2">&amp;</span><span class="self">self</span>) <span class="op">-&gt;</span> <span class="kw-2">*</span><span class="kw">const</span> <span class="ident">u8</span>;
}
<span class="kw">pub</span> <span class="kw">trait</span> <span class="ident">Wsr</span> {
<span class="kw">unsafe</span> <span class="kw">fn</span> <span class="ident">__wsr</span>(<span class="kw-2">&amp;</span><span class="self">self</span>, <span class="ident">value</span>: <span class="ident">u32</span>);
}
<span class="kw">pub</span> <span class="kw">trait</span> <span class="ident">Wsr64</span> {
<span class="kw">unsafe</span> <span class="kw">fn</span> <span class="ident">__wsr64</span>(<span class="kw-2">&amp;</span><span class="self">self</span>, <span class="ident">value</span>: <span class="ident">u64</span>);
}
<span class="kw">pub</span> <span class="kw">trait</span> <span class="ident">Wsrp</span> {
<span class="kw">unsafe</span> <span class="kw">fn</span> <span class="ident">__wsrp</span>(<span class="kw-2">&amp;</span><span class="self">self</span>, <span class="ident">value</span>: <span class="kw-2">*</span><span class="kw">const</span> <span class="ident">u8</span>);
}
}
</pre></div>
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