llvm/test/CodeGen/Hexagon/autohvx/isel-truncate.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -march=hexagon < %s | FileCheck %s

; Check that this compiles successfully.

target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
target triple = "hexagon"

@g0 = global <16 x i16> zeroinitializer, align 2

define void @fred(<16 x i32> %a0, <16 x i32> %a1) #0 {
; CHECK-LABEL: fred:
; CHECK:       // %bb.0: // %b0
; CHECK-NEXT:    {
; CHECK-NEXT:     r1:0 = combine(#-1,#32)
; CHECK-NEXT:     v2 = vxor(v2,v2)
; CHECK-NEXT:     q1 = vcmp.eq(v0.w,v1.w)
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     r7 = ##g0
; CHECK-NEXT:     q0 = vsetq(r0)
; CHECK-NEXT:     v0 = vmux(q1,v0,v2)
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     v30 = vand(q0,r1)
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     v0.h = vpacke(v0.w,v0.w)
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     v3 = vlalign(v2,v30,r7)
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     q2 = vand(v3,r1)
; CHECK-NEXT:     v1 = vlalign(v30,v2,r7)
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     q3 = vand(v1,r1)
; CHECK-NEXT:     v31 = vlalign(v2,v0,r7)
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     v0 = vlalign(v0,v2,r7)
; CHECK-NEXT:     if (q2) vmem(r7+#1) = v31
; CHECK-NEXT:    }
; CHECK-NEXT:    {
; CHECK-NEXT:     jumpr r31
; CHECK-NEXT:     if (q3) vmem(r7+#0) = v0
; CHECK-NEXT:    }
b0:
  %v0 = icmp eq <16 x i32> %a0, %a1
  %v1 = select <16 x i1> %v0, <16 x i32> %a0, <16 x i32> zeroinitializer
  %v2 = trunc <16 x i32> %v1 to <16 x i16>
  store <16 x i16> %v2, ptr @g0, align 2
  ret void
}

attributes #0 = { norecurse nounwind "target-cpu"="hexagonv65" "target-features"="+hvx-length64b,+hvxv65" }