llvm/test/CodeGen/AVR/llrint.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=avr -mcpu=atmega328p | FileCheck %s

define i64 @testmsxs_builtin(float %x) {
; CHECK-LABEL: testmsxs_builtin:
; CHECK:       ; %bb.0: ; %entry
; CHECK-NEXT:    call llrintf
; CHECK-NEXT:    ret
entry:
  %0 = tail call i64 @llvm.llrint.f32(float %x)
  ret i64 %0
}

define i64 @testmsxd_builtin(double %x) {
; CHECK-LABEL: testmsxd_builtin:
; CHECK:       ; %bb.0: ; %entry
; CHECK-NEXT:    call llrint
; CHECK-NEXT:    ret
entry:
  %0 = tail call i64 @llvm.llrint.f64(double %x)
  ret i64 %0
}

declare i64 @llvm.llrint.f32(float) nounwind readnone
declare i64 @llvm.llrint.f64(double) nounwind readnone