llvm/test/CodeGen/X86/GlobalISel/select-ext.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=i386-linux-gnu   -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=X86
# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=X64

--- |
  define i8 @test_zext_i1toi8(i1 %a) {
    %r = zext i1 %a to i8
    ret i8 %r
  }

  define i16 @test_zext_i1toi16(i1 %a) {
    %r = zext i1 %a to i16
    ret i16 %r
  }

  define i32 @test_zext_i1(i1 %a) {
    %r = zext i1 %a to i32
    ret i32 %r
  }

  define i32 @test_zext_i8(i8 %val) {
    %r = zext i8 %val to i32
    ret i32 %r
  }

  define i32 @test_zext_i16(i16 %val) {
    %r = zext i16 %val to i32
    ret i32 %r
  }

  define i32 @test_sext_i8(i8 %val) {
    %r = sext i8 %val to i32
    ret i32 %r
  }

  define i32 @test_sext_i16(i16 %val) {
    %r = sext i16 %val to i32
    ret i32 %r
  }

  define void @test_anyext_i1toi8() { ret void }
  define void @test_anyext_i1toi16() { ret void }
  define void @test_anyext_i1toi32() { ret void }
  define void @test_anyext_i8toi16() { ret void }
  define void @test_anyext_i8toi32() { ret void }
  define void @test_anyext_i16toi32() { ret void }

...
---
name:            test_zext_i1toi8
alignment:       16
legalized:       true
regBankSelected: true
registers:
  - { id: 0, class: gpr, preferred-register: '' }
  - { id: 1, class: gpr, preferred-register: '' }
  - { id: 2, class: gpr, preferred-register: '' }

body:             |
  bb.1 (%ir-block.0):
    liveins: $edi

    ; X86-LABEL: name: test_zext_i1toi8
    ; X86: [[COPY:%[0-9]+]]:gr32_abcd = COPY $edi
    ; X86-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
    ; X86-NEXT: [[AND8ri:%[0-9]+]]:gr8 = AND8ri [[COPY1]], 1, implicit-def $eflags
    ; X86-NEXT: $al = COPY [[AND8ri]]
    ; X86-NEXT: RET 0, implicit $al
    ; X64-LABEL: name: test_zext_i1toi8
    ; X64: [[COPY:%[0-9]+]]:gr32 = COPY $edi
    ; X64-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
    ; X64-NEXT: [[AND8ri:%[0-9]+]]:gr8 = AND8ri [[COPY1]], 1, implicit-def $eflags
    ; X64-NEXT: $al = COPY [[AND8ri]]
    ; X64-NEXT: RET 0, implicit $al
    %0(s32) = COPY $edi
    %1(s1) = G_TRUNC %0(s32)
    %2(s8) = G_ZEXT %1(s1)
    $al = COPY %2(s8)
    RET 0, implicit $al

...
---
name:            test_zext_i1toi16
alignment:       16
legalized:       true
regBankSelected: true
registers:
  - { id: 0, class: gpr, preferred-register: '' }
  - { id: 1, class: gpr, preferred-register: '' }
  - { id: 2, class: gpr, preferred-register: '' }

body:             |
  bb.1 (%ir-block.0):
    liveins: $edi

    ; X86-LABEL: name: test_zext_i1toi16
    ; X86: [[COPY:%[0-9]+]]:gr32_abcd = COPY $edi
    ; X86-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
    ; X86-NEXT: [[DEF:%[0-9]+]]:gr16 = IMPLICIT_DEF
    ; X86-NEXT: [[INSERT_SUBREG:%[0-9]+]]:gr16 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.sub_8bit
    ; X86-NEXT: [[AND16ri_:%[0-9]+]]:gr16 = AND16ri [[INSERT_SUBREG]], 1, implicit-def $eflags
    ; X86-NEXT: $ax = COPY [[AND16ri_]]
    ; X86-NEXT: RET 0, implicit $ax
    ; X64-LABEL: name: test_zext_i1toi16
    ; X64: [[COPY:%[0-9]+]]:gr32 = COPY $edi
    ; X64-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
    ; X64-NEXT: [[DEF:%[0-9]+]]:gr16 = IMPLICIT_DEF
    ; X64-NEXT: [[INSERT_SUBREG:%[0-9]+]]:gr16 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.sub_8bit
    ; X64-NEXT: [[AND16ri_:%[0-9]+]]:gr16 = AND16ri [[INSERT_SUBREG]], 1, implicit-def $eflags
    ; X64-NEXT: $ax = COPY [[AND16ri_]]
    ; X64-NEXT: RET 0, implicit $ax
    %0(s32) = COPY $edi
    %1(s1) = G_TRUNC %0(s32)
    %2(s16) = G_ZEXT %1(s1)
    $ax = COPY %2(s16)
    RET 0, implicit $ax

...
---
name:            test_zext_i1
alignment:       16
legalized:       true
regBankSelected: true
registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }
  - { id: 2, class: gpr }

body:             |
  bb.1 (%ir-block.0):
    liveins: $edi

    ; X86-LABEL: name: test_zext_i1
    ; X86: [[COPY:%[0-9]+]]:gr32_abcd = COPY $edi
    ; X86-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
    ; X86-NEXT: [[DEF:%[0-9]+]]:gr32 = IMPLICIT_DEF
    ; X86-NEXT: [[INSERT_SUBREG:%[0-9]+]]:gr32 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.sub_8bit
    ; X86-NEXT: [[AND32ri_:%[0-9]+]]:gr32 = AND32ri [[INSERT_SUBREG]], 1, implicit-def $eflags
    ; X86-NEXT: $eax = COPY [[AND32ri_]]
    ; X86-NEXT: RET 0, implicit $eax
    ; X64-LABEL: name: test_zext_i1
    ; X64: [[COPY:%[0-9]+]]:gr32 = COPY $edi
    ; X64-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
    ; X64-NEXT: [[DEF:%[0-9]+]]:gr32 = IMPLICIT_DEF
    ; X64-NEXT: [[INSERT_SUBREG:%[0-9]+]]:gr32 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.sub_8bit
    ; X64-NEXT: [[AND32ri_:%[0-9]+]]:gr32 = AND32ri [[INSERT_SUBREG]], 1, implicit-def $eflags
    ; X64-NEXT: $eax = COPY [[AND32ri_]]
    ; X64-NEXT: RET 0, implicit $eax
    %0(s32) = COPY $edi
    %1(s1) = G_TRUNC %0(s32)
    %2(s32) = G_ZEXT %1(s1)
    $eax = COPY %2(s32)
    RET 0, implicit $eax

...
---
name:            test_zext_i8
alignment:       16
legalized:       true
regBankSelected: true
registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }

body:             |
  bb.1 (%ir-block.0):
    liveins: $edi

    ; X86-LABEL: name: test_zext_i8
    ; X86: [[COPY:%[0-9]+]]:gr8 = COPY $dil
    ; X86-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY]]
    ; X86-NEXT: $eax = COPY [[MOVZX32rr8_]]
    ; X86-NEXT: RET 0, implicit $eax
    ; X64-LABEL: name: test_zext_i8
    ; X64: [[COPY:%[0-9]+]]:gr8 = COPY $dil
    ; X64-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY]]
    ; X64-NEXT: $eax = COPY [[MOVZX32rr8_]]
    ; X64-NEXT: RET 0, implicit $eax
    %0(s8) = COPY $dil
    %1(s32) = G_ZEXT %0(s8)
    $eax = COPY %1(s32)
    RET 0, implicit $eax

...
---
name:            test_zext_i16
alignment:       16
legalized:       true
regBankSelected: true
registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }

body:             |
  bb.1 (%ir-block.0):
    liveins: $edi

    ; X86-LABEL: name: test_zext_i16
    ; X86: [[COPY:%[0-9]+]]:gr16 = COPY $di
    ; X86-NEXT: [[MOVZX32rr16_:%[0-9]+]]:gr32 = MOVZX32rr16 [[COPY]]
    ; X86-NEXT: $eax = COPY [[MOVZX32rr16_]]
    ; X86-NEXT: RET 0, implicit $eax
    ; X64-LABEL: name: test_zext_i16
    ; X64: [[COPY:%[0-9]+]]:gr16 = COPY $di
    ; X64-NEXT: [[MOVZX32rr16_:%[0-9]+]]:gr32 = MOVZX32rr16 [[COPY]]
    ; X64-NEXT: $eax = COPY [[MOVZX32rr16_]]
    ; X64-NEXT: RET 0, implicit $eax
    %0(s16) = COPY $di
    %1(s32) = G_ZEXT %0(s16)
    $eax = COPY %1(s32)
    RET 0, implicit $eax

...
---
name:            test_sext_i8
alignment:       16
legalized:       true
regBankSelected: true
registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }

body:             |
  bb.1 (%ir-block.0):
    liveins: $edi

    ; X86-LABEL: name: test_sext_i8
    ; X86: [[COPY:%[0-9]+]]:gr8 = COPY $dil
    ; X86-NEXT: [[MOVSX32rr8_:%[0-9]+]]:gr32 = MOVSX32rr8 [[COPY]]
    ; X86-NEXT: $eax = COPY [[MOVSX32rr8_]]
    ; X86-NEXT: RET 0, implicit $eax
    ; X64-LABEL: name: test_sext_i8
    ; X64: [[COPY:%[0-9]+]]:gr8 = COPY $dil
    ; X64-NEXT: [[MOVSX32rr8_:%[0-9]+]]:gr32 = MOVSX32rr8 [[COPY]]
    ; X64-NEXT: $eax = COPY [[MOVSX32rr8_]]
    ; X64-NEXT: RET 0, implicit $eax
    %0(s8) = COPY $dil
    %1(s32) = G_SEXT %0(s8)
    $eax = COPY %1(s32)
    RET 0, implicit $eax

...
---
name:            test_sext_i16
alignment:       16
legalized:       true
regBankSelected: true
registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }

body:             |
  bb.1 (%ir-block.0):
    liveins: $edi

    ; X86-LABEL: name: test_sext_i16
    ; X86: [[COPY:%[0-9]+]]:gr16 = COPY $di
    ; X86-NEXT: [[MOVSX32rr16_:%[0-9]+]]:gr32 = MOVSX32rr16 [[COPY]]
    ; X86-NEXT: $eax = COPY [[MOVSX32rr16_]]
    ; X86-NEXT: RET 0, implicit $eax
    ; X64-LABEL: name: test_sext_i16
    ; X64: [[COPY:%[0-9]+]]:gr16 = COPY $di
    ; X64-NEXT: [[MOVSX32rr16_:%[0-9]+]]:gr32 = MOVSX32rr16 [[COPY]]
    ; X64-NEXT: $eax = COPY [[MOVSX32rr16_]]
    ; X64-NEXT: RET 0, implicit $eax
    %0(s16) = COPY $di
    %1(s32) = G_SEXT %0(s16)
    $eax = COPY %1(s32)
    RET 0, implicit $eax

...
---
name:            test_anyext_i1toi8
alignment:       16
legalized:       true
regBankSelected: true
registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }
  - { id: 2, class: gpr }

body:             |
  bb.1 (%ir-block.0):
    liveins: $edi

    ; X86-LABEL: name: test_anyext_i1toi8
    ; X86: [[COPY:%[0-9]+]]:gr32_abcd = COPY $edi
    ; X86-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
    ; X86-NEXT: $al = COPY [[COPY1]]
    ; X86-NEXT: RET 0, implicit $al
    ; X64-LABEL: name: test_anyext_i1toi8
    ; X64: [[COPY:%[0-9]+]]:gr32 = COPY $edi
    ; X64-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
    ; X64-NEXT: $al = COPY [[COPY1]]
    ; X64-NEXT: RET 0, implicit $al
    %0(s32) = COPY $edi
    %1(s1) = G_TRUNC %0(s32)
    %2(s8) = G_ANYEXT %1(s1)
    $al = COPY %2(s8)
    RET 0, implicit $al
...
---
name:            test_anyext_i1toi16
alignment:       16
legalized:       true
regBankSelected: true
registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }
  - { id: 2, class: gpr }

body:             |
  bb.1 (%ir-block.0):
    liveins: $edi

    ; X86-LABEL: name: test_anyext_i1toi16
    ; X86: [[COPY:%[0-9]+]]:gr32_abcd = COPY $edi
    ; X86-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
    ; X86-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr16 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_8bit
    ; X86-NEXT: $ax = COPY [[SUBREG_TO_REG]]
    ; X86-NEXT: RET 0, implicit $ax
    ; X64-LABEL: name: test_anyext_i1toi16
    ; X64: [[COPY:%[0-9]+]]:gr32 = COPY $edi
    ; X64-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
    ; X64-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr16 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_8bit
    ; X64-NEXT: $ax = COPY [[SUBREG_TO_REG]]
    ; X64-NEXT: RET 0, implicit $ax
    %0(s32) = COPY $edi
    %1(s1) = G_TRUNC %0(s32)
    %2(s16) = G_ANYEXT %1(s1)
    $ax = COPY %2(s16)
    RET 0, implicit $ax
...
---
name:            test_anyext_i1toi32
alignment:       16
legalized:       true
regBankSelected: true
registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }
  - { id: 2, class: gpr }

body:             |
  bb.1 (%ir-block.0):
    liveins: $edi

    ; X86-LABEL: name: test_anyext_i1toi32
    ; X86: [[COPY:%[0-9]+]]:gr32_abcd = COPY $edi
    ; X86-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
    ; X86-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_8bit
    ; X86-NEXT: $eax = COPY [[SUBREG_TO_REG]]
    ; X86-NEXT: RET 0, implicit $eax
    ; X64-LABEL: name: test_anyext_i1toi32
    ; X64: [[COPY:%[0-9]+]]:gr32 = COPY $edi
    ; X64-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
    ; X64-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr32 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_8bit
    ; X64-NEXT: $eax = COPY [[SUBREG_TO_REG]]
    ; X64-NEXT: RET 0, implicit $eax
    %0(s32) = COPY $edi
    %1(s1) = G_TRUNC %0(s32)
    %2(s32) = G_ANYEXT %1(s1)
    $eax = COPY %2(s32)
    RET 0, implicit $eax
...
---
name:            test_anyext_i8toi16
alignment:       16
legalized:       true
regBankSelected: true
registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }
  - { id: 2, class: gpr }

body:             |
  bb.1 (%ir-block.0):
    liveins: $edi

    ; X86-LABEL: name: test_anyext_i8toi16
    ; X86: [[COPY:%[0-9]+]]:gr32 = COPY $edi
    ; X86-NEXT: [[COPY1:%[0-9]+]]:gr32_abcd = COPY [[COPY]]
    ; X86-NEXT: [[COPY2:%[0-9]+]]:gr8_abcd_l = COPY [[COPY1]].sub_8bit
    ; X86-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY2]]
    ; X86-NEXT: [[COPY3:%[0-9]+]]:gr16 = COPY [[MOVZX32rr8_]].sub_16bit
    ; X86-NEXT: $ax = COPY [[COPY3]]
    ; X86-NEXT: RET 0, implicit $ax
    ; X64-LABEL: name: test_anyext_i8toi16
    ; X64: [[COPY:%[0-9]+]]:gr32 = COPY $edi
    ; X64-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
    ; X64-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY1]]
    ; X64-NEXT: [[COPY2:%[0-9]+]]:gr16 = COPY [[MOVZX32rr8_]].sub_16bit
    ; X64-NEXT: $ax = COPY [[COPY2]]
    ; X64-NEXT: RET 0, implicit $ax
    %0(s32) = COPY $edi
    %1(s8) = G_TRUNC %0(s32)
    %2(s16) = G_ANYEXT %1(s8)
    $ax = COPY %2(s16)
    RET 0, implicit $ax
...
---
name:            test_anyext_i8toi32
alignment:       16
legalized:       true
regBankSelected: true
registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }
  - { id: 2, class: gpr }

body:             |
  bb.1 (%ir-block.0):
    liveins: $edi

    ; X86-LABEL: name: test_anyext_i8toi32
    ; X86: [[COPY:%[0-9]+]]:gr32 = COPY $edi
    ; X86-NEXT: [[COPY1:%[0-9]+]]:gr32_abcd = COPY [[COPY]]
    ; X86-NEXT: [[COPY2:%[0-9]+]]:gr8_abcd_l = COPY [[COPY1]].sub_8bit
    ; X86-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY2]]
    ; X86-NEXT: $eax = COPY [[MOVZX32rr8_]]
    ; X86-NEXT: RET 0, implicit $eax
    ; X64-LABEL: name: test_anyext_i8toi32
    ; X64: [[COPY:%[0-9]+]]:gr32 = COPY $edi
    ; X64-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
    ; X64-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY1]]
    ; X64-NEXT: $eax = COPY [[MOVZX32rr8_]]
    ; X64-NEXT: RET 0, implicit $eax
    %0(s32) = COPY $edi
    %1(s8) = G_TRUNC %0(s32)
    %2(s32) = G_ANYEXT %1(s8)
    $eax = COPY %2(s32)
    RET 0, implicit $eax
...
---
name:            test_anyext_i16toi32
alignment:       16
legalized:       true
regBankSelected: true
registers:
  - { id: 0, class: gpr }
  - { id: 1, class: gpr }
  - { id: 2, class: gpr }

body:             |
  bb.1 (%ir-block.0):
    liveins: $edi

    ; X86-LABEL: name: test_anyext_i16toi32
    ; X86: [[COPY:%[0-9]+]]:gr32 = COPY $edi
    ; X86-NEXT: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
    ; X86-NEXT: [[DEF:%[0-9]+]]:low32_addr_access_rbp = IMPLICIT_DEF
    ; X86-NEXT: [[INSERT_SUBREG:%[0-9]+]]:low32_addr_access_rbp = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.sub_16bit
    ; X86-NEXT: $eax = COPY [[INSERT_SUBREG]]
    ; X86-NEXT: RET 0, implicit $eax
    ; X64-LABEL: name: test_anyext_i16toi32
    ; X64: [[COPY:%[0-9]+]]:gr32 = COPY $edi
    ; X64-NEXT: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
    ; X64-NEXT: [[DEF:%[0-9]+]]:low32_addr_access_rbp = IMPLICIT_DEF
    ; X64-NEXT: [[INSERT_SUBREG:%[0-9]+]]:low32_addr_access_rbp = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.sub_16bit
    ; X64-NEXT: $eax = COPY [[INSERT_SUBREG]]
    ; X64-NEXT: RET 0, implicit $eax
    %0(s32) = COPY $edi
    %1(s16) = G_TRUNC %0(s32)
    %2(s32) = G_ANYEXT %1(s16)
    $eax = COPY %2(s32)
    RET 0, implicit $eax
...