llvm/test/Transforms/InstCombine/vec_udiv_to_shift.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
; RUN: opt < %s -passes=instcombine -S | FileCheck %s

define <8 x i16> @udiv_vec8x16(<8 x i16> %var) {
; CHECK-LABEL: define <8 x i16> @udiv_vec8x16(
; CHECK-SAME: <8 x i16> [[VAR:%.*]]) {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    [[TMP0:%.*]] = lshr <8 x i16> [[VAR]], splat (i16 5)
; CHECK-NEXT:    ret <8 x i16> [[TMP0]]
;
entry:
%0 = udiv <8 x i16> %var, <i16 32, i16 32, i16 32, i16 32, i16 32, i16 32, i16 32, i16 32>
ret <8 x i16> %0
}

define <4 x i32> @udiv_vec4x32(<4 x i32> %var) {
; CHECK-LABEL: define <4 x i32> @udiv_vec4x32(
; CHECK-SAME: <4 x i32> [[VAR:%.*]]) {
; CHECK-NEXT:  [[ENTRY:.*:]]
; CHECK-NEXT:    [[TMP0:%.*]] = lshr <4 x i32> [[VAR]], splat (i32 4)
; CHECK-NEXT:    ret <4 x i32> [[TMP0]]
;
entry:
%0 = udiv <4 x i32> %var, <i32 16, i32 16, i32 16, i32 16>
ret <4 x i32> %0
}