llvm/test/CodeGen/RISCV/branch-opt.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
; RUN: llc -mtriple=riscv32 -O2 -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -O2 -verify-machineinstrs < %s | FileCheck %s

define void @u_case1_a(ptr %a, i32 signext %b, ptr %c, ptr %d) {
; CHECK-LABEL: u_case1_a:
; CHECK:       # %bb.0:
; CHECK-NEXT:    li a4, 32
; CHECK-NEXT:    sw a4, 0(a0)
; CHECK-NEXT:    bgeu a1, a4, .LBB0_2
; CHECK-NEXT:  # %bb.1: # %block1
; CHECK-NEXT:    sw a1, 0(a2)
; CHECK-NEXT:    ret
; CHECK-NEXT:  .LBB0_2: # %block2
; CHECK-NEXT:    li a0, 87
; CHECK-NEXT:    sw a0, 0(a3)
; CHECK-NEXT:    ret
  store i32 32, ptr %a
  %p = icmp ule i32 %b, 31
  br i1 %p, label %block1, label %block2

block1:                                           ; preds = %0
  store i32 %b, ptr %c
  br label %end_block

block2:                                           ; preds = %0
  store i32 87, ptr %d
  br label %end_block

end_block:                                        ; preds = %block2, %block1
  ret void
}

define void @case1_a(ptr %a, i32 signext %b, ptr %c, ptr %d) {
; CHECK-LABEL: case1_a:
; CHECK:       # %bb.0:
; CHECK-NEXT:    li a4, -1
; CHECK-NEXT:    sw a4, 0(a0)
; CHECK-NEXT:    bge a1, a4, .LBB1_2
; CHECK-NEXT:  # %bb.1: # %block1
; CHECK-NEXT:    sw a1, 0(a2)
; CHECK-NEXT:    ret
; CHECK-NEXT:  .LBB1_2: # %block2
; CHECK-NEXT:    li a0, 87
; CHECK-NEXT:    sw a0, 0(a3)
; CHECK-NEXT:    ret
  store i32 -1, ptr %a
  %p = icmp sle i32 %b, -2
  br i1 %p, label %block1, label %block2

block1:                                           ; preds = %0
  store i32 %b, ptr %c
  br label %end_block

block2:                                           ; preds = %0
  store i32 87, ptr %d
  br label %end_block

end_block:                                        ; preds = %block2, %block1
  ret void
}

define void @u_case2_a(ptr %a, i32 signext %b, ptr %c, ptr %d) {
; CHECK-LABEL: u_case2_a:
; CHECK:       # %bb.0:
; CHECK-NEXT:    li a4, 32
; CHECK-NEXT:    sw a4, 0(a0)
; CHECK-NEXT:    bgeu a4, a1, .LBB2_2
; CHECK-NEXT:  # %bb.1: # %block1
; CHECK-NEXT:    sw a1, 0(a2)
; CHECK-NEXT:    ret
; CHECK-NEXT:  .LBB2_2: # %block2
; CHECK-NEXT:    li a0, 87
; CHECK-NEXT:    sw a0, 0(a3)
; CHECK-NEXT:    ret
  store i32 32, ptr %a
  %p = icmp uge i32 %b, 33
  br i1 %p, label %block1, label %block2

block1:                                           ; preds = %0
  store i32 %b, ptr %c
  br label %end_block

block2:                                           ; preds = %0
  store i32 87, ptr %d
  br label %end_block

end_block:                                        ; preds = %block2, %block1
  ret void
}

define void @case2_a(ptr %a, i32 signext %b, ptr %c, ptr %d) {
; CHECK-LABEL: case2_a:
; CHECK:       # %bb.0:
; CHECK-NEXT:    li a4, -4
; CHECK-NEXT:    sw a4, 0(a0)
; CHECK-NEXT:    bge a4, a1, .LBB3_2
; CHECK-NEXT:  # %bb.1: # %block1
; CHECK-NEXT:    sw a1, 0(a2)
; CHECK-NEXT:    ret
; CHECK-NEXT:  .LBB3_2: # %block2
; CHECK-NEXT:    li a0, 87
; CHECK-NEXT:    sw a0, 0(a3)
; CHECK-NEXT:    ret
  store i32 -4, ptr %a
  %p = icmp sge i32 %b, -3
  br i1 %p, label %block1, label %block2

block1:                                           ; preds = %0
  store i32 %b, ptr %c
  br label %end_block

block2:                                           ; preds = %0
  store i32 87, ptr %d
  br label %end_block

end_block:                                        ; preds = %block2, %block1
  ret void
}