llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/is-fpclass-f16-rv32.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 3
# RUN: llc -mtriple=riscv32 -mattr=+zfh -run-pass=instruction-select -verify-machineinstrs %s -o - | \
# RUN: FileCheck %s

---
name:            is_fpclass_f16
legalized:       true
regBankSelected: true
body:             |
  bb.0:
    liveins: $f10_h

    ; CHECK-LABEL: name: is_fpclass_f16
    ; CHECK: liveins: $f10_h
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
    ; CHECK-NEXT: [[FCLASS_H:%[0-9]+]]:gpr = FCLASS_H [[COPY]]
    ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[FCLASS_H]], 152
    ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU $x0, [[ANDI]]
    ; CHECK-NEXT: $x10 = COPY [[SLTU]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:fprb(s16) = COPY $f10_h
    %3:gprb(s32) = G_CONSTANT i32 152
    %4:gprb(s32) = G_CONSTANT i32 0
    %5:gprb(s32) = G_FCLASS %0(s16)
    %6:gprb(s32) = G_AND %5, %3
    %7:gprb(s32) = G_ICMP intpred(ne), %6(s32), %4
    $x10 = COPY %7(s32)
    PseudoRET implicit $x10
...
---
name:            is_fpclass_f16_onehot
legalized:       true
regBankSelected: true
body:             |
  bb.0:
    liveins: $f10_h

    ; CHECK-LABEL: name: is_fpclass_f16_onehot
    ; CHECK: liveins: $f10_h
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
    ; CHECK-NEXT: [[FCLASS_H:%[0-9]+]]:gpr = FCLASS_H [[COPY]]
    ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[FCLASS_H]], 256
    ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU $x0, [[ANDI]]
    ; CHECK-NEXT: $x10 = COPY [[SLTU]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:fprb(s16) = COPY $f10_h
    %3:gprb(s32) = G_CONSTANT i32 256
    %4:gprb(s32) = G_CONSTANT i32 0
    %5:gprb(s32) = G_FCLASS %0(s16)
    %6:gprb(s32) = G_AND %5, %3
    %7:gprb(s32) = G_ICMP intpred(ne), %6(s32), %4
    $x10 = COPY %7(s32)
    PseudoRET implicit $x10
...
---
name:            is_fpclass_f16_one
legalized:       true
regBankSelected: true
body:             |
  bb.0:
    liveins: $f10_h

    ; CHECK-LABEL: name: is_fpclass_f16_one
    ; CHECK: liveins: $f10_h
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $f10_h
    ; CHECK-NEXT: [[FCLASS_H:%[0-9]+]]:gpr = FCLASS_H [[COPY]]
    ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[FCLASS_H]], 1
    ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU $x0, [[ANDI]]
    ; CHECK-NEXT: $x10 = COPY [[SLTU]]
    ; CHECK-NEXT: PseudoRET implicit $x10
    %0:fprb(s16) = COPY $f10_h
    %3:gprb(s32) = G_CONSTANT i32 1
    %4:gprb(s32) = G_CONSTANT i32 0
    %5:gprb(s32) = G_FCLASS %0(s16)
    %6:gprb(s32) = G_AND %5, %3
    %7:gprb(s32) = G_ICMP intpred(ne), %6(s32), %4
    $x10 = COPY %7(s32)
    PseudoRET implicit $x10
...