llvm/test/CodeGen/PowerPC/early-ifcvt-no-isel.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
# RUN: llc -mtriple=powerpc64-ibm-aix -mcpu=pwr7 -simplify-mir -verify-machineinstrs \
# RUN:   -run-pass=early-ifcvt %s -o - | FileCheck %s
# RUN: llc -mtriple=powerpc64-ibm-aix -mcpu=pwr7 -simplify-mir -verify-each \
# RUN:   -passes=early-ifcvt %s -o - | FileCheck %s

--- |
  source_filename = "<stdin>"

  define signext i32 @foo(ptr nocapture noundef %dummy) #0 {
  entry:
    %0 = load i32, ptr %dummy, align 4
    %cmp = icmp slt i32 %0, 750
    %inc = add nsw i32 %0, 1
    %storemerge = select i1 %cmp, i32 %inc, i32 1
    store i32 %storemerge, ptr %dummy, align 4
    ret i32 0
  }

  attributes #0 = { "target-features"="-isel" }

...
---
name:            foo
alignment:       16
tracksRegLiveness: true
registers:
  - { id: 0, class: g8rc_and_g8rc_nox0 }
  - { id: 1, class: gprc_and_gprc_nor0 }
  - { id: 2, class: gprc_and_gprc_nor0 }
  - { id: 3, class: crrc }
  - { id: 4, class: gprc_and_gprc_nor0 }
  - { id: 5, class: gprc }
  - { id: 6, class: g8rc }
liveins:
  - { reg: '$x3', virtual-reg: '%0' }
frameInfo:
  maxAlignment:    1
machineFunctionInfo: {}
body:             |
  ; CHECK-LABEL: name: foo
  ; CHECK: bb.0.entry:
  ; CHECK-NEXT:   successors: %bb.1, %bb.2
  ; CHECK-NEXT:   liveins: $x3
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY $x3
  ; CHECK-NEXT:   [[LWZ:%[0-9]+]]:gprc_and_gprc_nor0 = LWZ 0, [[COPY]] :: (load (s32) from %ir.dummy)
  ; CHECK-NEXT:   [[ADDI:%[0-9]+]]:gprc_and_gprc_nor0 = nsw ADDI [[LWZ]], 1
  ; CHECK-NEXT:   [[CMPWI:%[0-9]+]]:crrc = CMPWI [[LWZ]], 750
  ; CHECK-NEXT:   [[LI:%[0-9]+]]:gprc_and_gprc_nor0 = LI 1
  ; CHECK-NEXT:   BCC 12, [[CMPWI]], %bb.2
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1.entry:
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2.entry:
  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:gprc = PHI [[LI]], %bb.1, [[ADDI]], %bb.0
  ; CHECK-NEXT:   STW killed [[PHI]], 0, [[COPY]] :: (store (s32) into %ir.dummy)
  ; CHECK-NEXT:   [[LI8_:%[0-9]+]]:g8rc = LI8 0
  ; CHECK-NEXT:   $x3 = COPY [[LI8_]]
  ; CHECK-NEXT:   BLR8 implicit $lr8, implicit $rm, implicit $x3
  bb.0.entry:
    successors: %bb.1, %bb.2
    liveins: $x3

    %0:g8rc_and_g8rc_nox0 = COPY $x3
    %1:gprc_and_gprc_nor0 = LWZ 0, %0 :: (load (s32) from %ir.dummy)
    %2:gprc_and_gprc_nor0 = nsw ADDI %1, 1
    %3:crrc = CMPWI %1, 750
    %4:gprc_and_gprc_nor0 = LI 1
    BCC 12, %3, %bb.2

  bb.1.entry:

  bb.2.entry:
    %5:gprc = PHI %4, %bb.1, %2, %bb.0
    STW killed %5, 0, %0 :: (store (s32) into %ir.dummy)
    %6:g8rc = LI8 0
    $x3 = COPY %6
    BLR8 implicit $lr8, implicit $rm, implicit $x3

...