llvm/test/CodeGen/NVPTX/f32-ex2.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mcpu=sm_50 -mattr=+ptx32 | FileCheck --check-prefixes=CHECK %s
; RUN: %if ptxas-11.0 %{ llc < %s -mtriple=nvptx64 -mcpu=sm_50 -mattr=+ptx32 | %ptxas-verify -arch=sm_50 %}
target triple = "nvptx-nvidia-cuda"

declare float @llvm.nvvm.ex2.approx.f(float)

; CHECK-LABEL: ex2_float
define float @ex2_float(float %0) {
; CHECK-LABEL: ex2_float(
; CHECK:       {
; CHECK-NEXT:    .reg .f32 %f<3>;
; CHECK-EMPTY:
; CHECK-NEXT:  // %bb.0:
; CHECK-NEXT:    ld.param.f32 %f1, [ex2_float_param_0];
; CHECK-NEXT:    ex2.approx.f32 %f2, %f1;
; CHECK-NEXT:    st.param.f32 [func_retval0], %f2;
; CHECK-NEXT:    ret;
  %res = call float @llvm.nvvm.ex2.approx.f(float %0)
  ret float %res
}

; CHECK-LABEL: ex2_float_ftz
define float @ex2_float_ftz(float %0) {
; CHECK-LABEL: ex2_float_ftz(
; CHECK:       {
; CHECK-NEXT:    .reg .f32 %f<3>;
; CHECK-EMPTY:
; CHECK-NEXT:  // %bb.0:
; CHECK-NEXT:    ld.param.f32 %f1, [ex2_float_ftz_param_0];
; CHECK-NEXT:    ex2.approx.ftz.f32 %f2, %f1;
; CHECK-NEXT:    st.param.f32 [func_retval0], %f2;
; CHECK-NEXT:    ret;
  %res = call float @llvm.nvvm.ex2.approx.ftz.f(float %0)
  ret float %res
}