llvm/test/CodeGen/LoongArch/lsx/intrinsic-sllwil.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s

declare <8 x i16> @llvm.loongarch.lsx.vsllwil.h.b(<16 x i8>, i32)

define <8 x i16> @lsx_vsllwil_h_b(<16 x i8> %va) nounwind {
; CHECK-LABEL: lsx_vsllwil_h_b:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsllwil.h.b $vr0, $vr0, 1
; CHECK-NEXT:    ret
entry:
  %res = call <8 x i16> @llvm.loongarch.lsx.vsllwil.h.b(<16 x i8> %va, i32 1)
  ret <8 x i16> %res
}

declare <4 x i32> @llvm.loongarch.lsx.vsllwil.w.h(<8 x i16>, i32)

define <4 x i32> @lsx_vsllwil_w_h(<8 x i16> %va) nounwind {
; CHECK-LABEL: lsx_vsllwil_w_h:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsllwil.w.h $vr0, $vr0, 1
; CHECK-NEXT:    ret
entry:
  %res = call <4 x i32> @llvm.loongarch.lsx.vsllwil.w.h(<8 x i16> %va, i32 1)
  ret <4 x i32> %res
}

declare <2 x i64> @llvm.loongarch.lsx.vsllwil.d.w(<4 x i32>, i32)

define <2 x i64> @lsx_vsllwil_d_w(<4 x i32> %va) nounwind {
; CHECK-LABEL: lsx_vsllwil_d_w:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsllwil.d.w $vr0, $vr0, 1
; CHECK-NEXT:    ret
entry:
  %res = call <2 x i64> @llvm.loongarch.lsx.vsllwil.d.w(<4 x i32> %va, i32 1)
  ret <2 x i64> %res
}

declare <8 x i16> @llvm.loongarch.lsx.vsllwil.hu.bu(<16 x i8>, i32)

define <8 x i16> @lsx_vsllwil_hu_bu(<16 x i8> %va) nounwind {
; CHECK-LABEL: lsx_vsllwil_hu_bu:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsllwil.hu.bu $vr0, $vr0, 7
; CHECK-NEXT:    ret
entry:
  %res = call <8 x i16> @llvm.loongarch.lsx.vsllwil.hu.bu(<16 x i8> %va, i32 7)
  ret <8 x i16> %res
}

declare <4 x i32> @llvm.loongarch.lsx.vsllwil.wu.hu(<8 x i16>, i32)

define <4 x i32> @lsx_vsllwil_wu_hu(<8 x i16> %va) nounwind {
; CHECK-LABEL: lsx_vsllwil_wu_hu:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsllwil.wu.hu $vr0, $vr0, 15
; CHECK-NEXT:    ret
entry:
  %res = call <4 x i32> @llvm.loongarch.lsx.vsllwil.wu.hu(<8 x i16> %va, i32 15)
  ret <4 x i32> %res
}

declare <2 x i64> @llvm.loongarch.lsx.vsllwil.du.wu(<4 x i32>, i32)

define <2 x i64> @lsx_vsllwil_du_wu(<4 x i32> %va) nounwind {
; CHECK-LABEL: lsx_vsllwil_du_wu:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsllwil.du.wu $vr0, $vr0, 31
; CHECK-NEXT:    ret
entry:
  %res = call <2 x i64> @llvm.loongarch.lsx.vsllwil.du.wu(<4 x i32> %va, i32 31)
  ret <2 x i64> %res
}