llvm/test/CodeGen/AMDGPU/load-store-opt-addc0.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=amdgcn -mcpu=gfx900 -run-pass=si-load-store-opt -o - %s | FileCheck --check-prefix=GCN %s

# This used to crash

---
name:            analyze_addc_0_0
body:             |
  bb.1.entry:
    liveins: $vgpr0

    ; GCN-LABEL: name: analyze_addc_0_0
    ; GCN: liveins: $vgpr0
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
    ; GCN-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY]], 16, 0, implicit $exec
    ; GCN-NEXT: [[V_ADDC_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADDC_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADDC_U32_e64 0, 0, killed [[V_ADD_CO_U32_e64_1]], 0, implicit $exec
    ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_ADD_CO_U32_e64_]], %subreg.sub0, [[V_ADDC_U32_e64_]], %subreg.sub1
    ; GCN-NEXT: [[GLOBAL_LOAD_DWORDX4_:%[0-9]+]]:vreg_128 = GLOBAL_LOAD_DWORDX4 [[REG_SEQUENCE]], 0, 0, implicit $exec
    %0:vgpr_32 = COPY $vgpr0
    %1:vgpr_32, %2:sreg_64_xexec = V_ADD_CO_U32_e64 %0, 16, 0, implicit $exec
    %3:vgpr_32, dead %26:sreg_64_xexec = V_ADDC_U32_e64 0, 0, killed %2, 0, implicit $exec
    %4:vreg_64 = REG_SEQUENCE %1, %subreg.sub0, %3, %subreg.sub1
    %5:vreg_128 = GLOBAL_LOAD_DWORDX4 %4, 0, 0, implicit $exec

...