llvm/test/CodeGen/AArch64/sve-scmp.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=aarch64 -mattr=+sve2 -verify-machineinstrs %s -o - | FileCheck %s

define <vscale x 8 x i8> @s_nxv8i8(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b) {
; CHECK-LABEL: s_nxv8i8:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    ptrue p0.h
; CHECK-NEXT:    sxtb z0.h, p0/m, z0.h
; CHECK-NEXT:    sxtb z1.h, p0/m, z1.h
; CHECK-NEXT:    cmpgt p1.h, p0/z, z0.h, z1.h
; CHECK-NEXT:    cmpgt p0.h, p0/z, z1.h, z0.h
; CHECK-NEXT:    mov z0.h, p1/z, #1 // =0x1
; CHECK-NEXT:    mov z0.h, p0/m, #-1 // =0xffffffffffffffff
; CHECK-NEXT:    ret
entry:
  %c = call <vscale x 8 x i8> @llvm.scmp(<vscale x 8 x i8> %a, <vscale x 8 x i8> %b)
  ret <vscale x 8 x i8> %c
}

define <vscale x 16 x i8> @s_nxv16i8(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
; CHECK-LABEL: s_nxv16i8:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    ptrue p0.b
; CHECK-NEXT:    cmpgt p1.b, p0/z, z0.b, z1.b
; CHECK-NEXT:    cmpgt p0.b, p0/z, z1.b, z0.b
; CHECK-NEXT:    mov z0.b, p1/z, #1 // =0x1
; CHECK-NEXT:    mov z0.b, p0/m, #-1 // =0xffffffffffffffff
; CHECK-NEXT:    ret
entry:
  %c = call <vscale x 16 x i8> @llvm.scmp(<vscale x 16 x i8> %a, <vscale x 16 x i8> %b)
  ret <vscale x 16 x i8> %c
}

define <vscale x 4 x i16> @s_nxv4i16(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b) {
; CHECK-LABEL: s_nxv4i16:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    ptrue p0.s
; CHECK-NEXT:    sxth z0.s, p0/m, z0.s
; CHECK-NEXT:    sxth z1.s, p0/m, z1.s
; CHECK-NEXT:    cmpgt p1.s, p0/z, z0.s, z1.s
; CHECK-NEXT:    cmpgt p0.s, p0/z, z1.s, z0.s
; CHECK-NEXT:    mov z0.s, p1/z, #1 // =0x1
; CHECK-NEXT:    mov z0.s, p0/m, #-1 // =0xffffffffffffffff
; CHECK-NEXT:    ret
entry:
  %c = call <vscale x 4 x i16> @llvm.scmp(<vscale x 4 x i16> %a, <vscale x 4 x i16> %b)
  ret <vscale x 4 x i16> %c
}

define <vscale x 8 x i16> @s_nxv8i16(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
; CHECK-LABEL: s_nxv8i16:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    ptrue p0.h
; CHECK-NEXT:    cmpgt p1.h, p0/z, z0.h, z1.h
; CHECK-NEXT:    cmpgt p0.h, p0/z, z1.h, z0.h
; CHECK-NEXT:    mov z0.h, p1/z, #1 // =0x1
; CHECK-NEXT:    mov z0.h, p0/m, #-1 // =0xffffffffffffffff
; CHECK-NEXT:    ret
entry:
  %c = call <vscale x 8 x i16> @llvm.scmp(<vscale x 8 x i16> %a, <vscale x 8 x i16> %b)
  ret <vscale x 8 x i16> %c
}

define <vscale x 16 x i16> @s_nxv16i16(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b) {
; CHECK-LABEL: s_nxv16i16:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    ptrue p0.h
; CHECK-NEXT:    cmpgt p1.h, p0/z, z0.h, z2.h
; CHECK-NEXT:    cmpgt p2.h, p0/z, z1.h, z3.h
; CHECK-NEXT:    cmpgt p3.h, p0/z, z2.h, z0.h
; CHECK-NEXT:    cmpgt p0.h, p0/z, z3.h, z1.h
; CHECK-NEXT:    mov z0.h, p1/z, #1 // =0x1
; CHECK-NEXT:    mov z1.h, p2/z, #1 // =0x1
; CHECK-NEXT:    mov z0.h, p3/m, #-1 // =0xffffffffffffffff
; CHECK-NEXT:    mov z1.h, p0/m, #-1 // =0xffffffffffffffff
; CHECK-NEXT:    ret
entry:
  %c = call <vscale x 16 x i16> @llvm.scmp(<vscale x 16 x i16> %a, <vscale x 16 x i16> %b)
  ret <vscale x 16 x i16> %c
}

define <vscale x 2 x i32> @s_nxv2i32(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b) {
; CHECK-LABEL: s_nxv2i32:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    ptrue p0.d
; CHECK-NEXT:    sxtw z0.d, p0/m, z0.d
; CHECK-NEXT:    sxtw z1.d, p0/m, z1.d
; CHECK-NEXT:    cmpgt p1.d, p0/z, z0.d, z1.d
; CHECK-NEXT:    cmpgt p0.d, p0/z, z1.d, z0.d
; CHECK-NEXT:    mov z0.d, p1/z, #1 // =0x1
; CHECK-NEXT:    mov z0.d, p0/m, #-1 // =0xffffffffffffffff
; CHECK-NEXT:    ret
entry:
  %c = call <vscale x 2 x i32> @llvm.scmp(<vscale x 2 x i32> %a, <vscale x 2 x i32> %b)
  ret <vscale x 2 x i32> %c
}

define <vscale x 4 x i32> @s_nxv4i32(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b) {
; CHECK-LABEL: s_nxv4i32:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    ptrue p0.s
; CHECK-NEXT:    cmpgt p1.s, p0/z, z0.s, z1.s
; CHECK-NEXT:    cmpgt p0.s, p0/z, z1.s, z0.s
; CHECK-NEXT:    mov z0.s, p1/z, #1 // =0x1
; CHECK-NEXT:    mov z0.s, p0/m, #-1 // =0xffffffffffffffff
; CHECK-NEXT:    ret
entry:
  %c = call <vscale x 4 x i32> @llvm.scmp(<vscale x 4 x i32> %a, <vscale x 4 x i32> %b)
  ret <vscale x 4 x i32> %c
}

define <vscale x 8 x i32> @s_nxv8i32(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b) {
; CHECK-LABEL: s_nxv8i32:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    ptrue p0.s
; CHECK-NEXT:    cmpgt p1.s, p0/z, z0.s, z2.s
; CHECK-NEXT:    cmpgt p2.s, p0/z, z1.s, z3.s
; CHECK-NEXT:    cmpgt p3.s, p0/z, z2.s, z0.s
; CHECK-NEXT:    cmpgt p0.s, p0/z, z3.s, z1.s
; CHECK-NEXT:    mov z0.s, p1/z, #1 // =0x1
; CHECK-NEXT:    mov z1.s, p2/z, #1 // =0x1
; CHECK-NEXT:    mov z0.s, p3/m, #-1 // =0xffffffffffffffff
; CHECK-NEXT:    mov z1.s, p0/m, #-1 // =0xffffffffffffffff
; CHECK-NEXT:    ret
entry:
  %c = call <vscale x 8 x i32> @llvm.scmp(<vscale x 8 x i32> %a, <vscale x 8 x i32> %b)
  ret <vscale x 8 x i32> %c
}

define <vscale x 2 x i64> @s_nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b) {
; CHECK-LABEL: s_nxv2i64:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    ptrue p0.d
; CHECK-NEXT:    cmpgt p1.d, p0/z, z0.d, z1.d
; CHECK-NEXT:    cmpgt p0.d, p0/z, z1.d, z0.d
; CHECK-NEXT:    mov z0.d, p1/z, #1 // =0x1
; CHECK-NEXT:    mov z0.d, p0/m, #-1 // =0xffffffffffffffff
; CHECK-NEXT:    ret
entry:
  %c = call <vscale x 2 x i64> @llvm.scmp(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b)
  ret <vscale x 2 x i64> %c
}

define <vscale x 4 x i64> @s_nxv4i64(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b) {
; CHECK-LABEL: s_nxv4i64:
; CHECK:       // %bb.0: // %entry
; CHECK-NEXT:    ptrue p0.d
; CHECK-NEXT:    cmpgt p1.d, p0/z, z0.d, z2.d
; CHECK-NEXT:    cmpgt p2.d, p0/z, z1.d, z3.d
; CHECK-NEXT:    cmpgt p3.d, p0/z, z2.d, z0.d
; CHECK-NEXT:    cmpgt p0.d, p0/z, z3.d, z1.d
; CHECK-NEXT:    mov z0.d, p1/z, #1 // =0x1
; CHECK-NEXT:    mov z1.d, p2/z, #1 // =0x1
; CHECK-NEXT:    mov z0.d, p3/m, #-1 // =0xffffffffffffffff
; CHECK-NEXT:    mov z1.d, p0/m, #-1 // =0xffffffffffffffff
; CHECK-NEXT:    ret
entry:
  %c = call <vscale x 4 x i64> @llvm.scmp(<vscale x 4 x i64> %a, <vscale x 4 x i64> %b)
  ret <vscale x 4 x i64> %c
}