llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-same-scope-diff-key.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -verify-machineinstrs -enable-machine-outliner -mtriple aarch64 %s -o - | \
; RUN:   FileCheck %s --check-prefixes CHECK,V8A
; RUN: llc -verify-machineinstrs -enable-machine-outliner -mtriple aarch64 -mattr=+v8.3a %s -o - | \
; RUN:   FileCheck %s --check-prefixes CHECK,V83A

define void @a() "sign-return-address"="all" {
; V8A-LABEL: a:
; V8A:       // %bb.0:
; V8A-NEXT:    hint #25
; V8A-NEXT:    .cfi_negate_ra_state
; V8A-NEXT:    sub sp, sp, #32
; V8A-NEXT:    .cfi_def_cfa_offset 32
; V8A-NEXT:    mov w8, #1 // =0x1
; V8A-NEXT:    mov w9, #2 // =0x2
; V8A-NEXT:    stp w9, w8, [sp, #24]
; V8A-NEXT:    mov w9, #3 // =0x3
; V8A-NEXT:    mov w8, #4 // =0x4
; V8A-NEXT:    stp w8, w9, [sp, #16]
; V8A-NEXT:    mov w9, #5 // =0x5
; V8A-NEXT:    mov w8, #6 // =0x6
; V8A-NEXT:    stp w8, w9, [sp, #8]
; V8A-NEXT:    add sp, sp, #32
; V8A-NEXT:    hint #29
; V8A-NEXT:    ret
;
; V83A-LABEL: a:
; V83A:       // %bb.0:
; V83A-NEXT:    paciasp
; V83A-NEXT:    .cfi_negate_ra_state
; V83A-NEXT:    sub sp, sp, #32
; V83A-NEXT:    .cfi_def_cfa_offset 32
; V83A-NEXT:    mov w8, #1 // =0x1
; V83A-NEXT:    mov w9, #2 // =0x2
; V83A-NEXT:    stp w9, w8, [sp, #24]
; V83A-NEXT:    mov w9, #3 // =0x3
; V83A-NEXT:    mov w8, #4 // =0x4
; V83A-NEXT:    stp w8, w9, [sp, #16]
; V83A-NEXT:    mov w9, #5 // =0x5
; V83A-NEXT:    mov w8, #6 // =0x6
; V83A-NEXT:    stp w8, w9, [sp, #8]
; V83A-NEXT:    add sp, sp, #32
; V83A-NEXT:    retaa
  %1 = alloca i32, align 4
  %2 = alloca i32, align 4
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  store i32 1, ptr %1, align 4
  store i32 2, ptr %2, align 4
  store i32 3, ptr %3, align 4
  store i32 4, ptr %4, align 4
  store i32 5, ptr %5, align 4
  store i32 6, ptr %6, align 4
  ret void
}

define void @b() "sign-return-address"="all" "sign-return-address-key"="b_key" {
; V8A-LABEL: b:
; V8A:       // %bb.0:
; V8A-NEXT:    .cfi_b_key_frame
; V8A-NEXT:    hint #27
; V8A-NEXT:    .cfi_negate_ra_state
; V8A-NEXT:    sub sp, sp, #32
; V8A-NEXT:    .cfi_def_cfa_offset 32
; V8A-NEXT:    mov w8, #1 // =0x1
; V8A-NEXT:    mov w9, #2 // =0x2
; V8A-NEXT:    stp w9, w8, [sp, #24]
; V8A-NEXT:    mov w9, #3 // =0x3
; V8A-NEXT:    mov w8, #4 // =0x4
; V8A-NEXT:    stp w8, w9, [sp, #16]
; V8A-NEXT:    mov w9, #5 // =0x5
; V8A-NEXT:    mov w8, #6 // =0x6
; V8A-NEXT:    stp w8, w9, [sp, #8]
; V8A-NEXT:    add sp, sp, #32
; V8A-NEXT:    hint #31
; V8A-NEXT:    ret
;
; V83A-LABEL: b:
; V83A:       // %bb.0:
; V83A-NEXT:    .cfi_b_key_frame
; V83A-NEXT:    pacibsp
; V83A-NEXT:    .cfi_negate_ra_state
; V83A-NEXT:    sub sp, sp, #32
; V83A-NEXT:    .cfi_def_cfa_offset 32
; V83A-NEXT:    mov w8, #1 // =0x1
; V83A-NEXT:    mov w9, #2 // =0x2
; V83A-NEXT:    stp w9, w8, [sp, #24]
; V83A-NEXT:    mov w9, #3 // =0x3
; V83A-NEXT:    mov w8, #4 // =0x4
; V83A-NEXT:    stp w8, w9, [sp, #16]
; V83A-NEXT:    mov w9, #5 // =0x5
; V83A-NEXT:    mov w8, #6 // =0x6
; V83A-NEXT:    stp w8, w9, [sp, #8]
; V83A-NEXT:    add sp, sp, #32
; V83A-NEXT:    retab
  %1 = alloca i32, align 4
  %2 = alloca i32, align 4
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  store i32 1, ptr %1, align 4
  store i32 2, ptr %2, align 4
  store i32 3, ptr %3, align 4
  store i32 4, ptr %4, align 4
  store i32 5, ptr %5, align 4
  store i32 6, ptr %6, align 4
  ret void
}

define void @c() "sign-return-address"="all" {
; V8A-LABEL: c:
; V8A:       // %bb.0:
; V8A-NEXT:    hint #25
; V8A-NEXT:    .cfi_negate_ra_state
; V8A-NEXT:    sub sp, sp, #32
; V8A-NEXT:    .cfi_def_cfa_offset 32
; V8A-NEXT:    mov w8, #1 // =0x1
; V8A-NEXT:    mov w9, #2 // =0x2
; V8A-NEXT:    stp w9, w8, [sp, #24]
; V8A-NEXT:    mov w9, #3 // =0x3
; V8A-NEXT:    mov w8, #4 // =0x4
; V8A-NEXT:    stp w8, w9, [sp, #16]
; V8A-NEXT:    mov w9, #5 // =0x5
; V8A-NEXT:    mov w8, #6 // =0x6
; V8A-NEXT:    stp w8, w9, [sp, #8]
; V8A-NEXT:    add sp, sp, #32
; V8A-NEXT:    hint #29
; V8A-NEXT:    ret
;
; V83A-LABEL: c:
; V83A:       // %bb.0:
; V83A-NEXT:    paciasp
; V83A-NEXT:    .cfi_negate_ra_state
; V83A-NEXT:    sub sp, sp, #32
; V83A-NEXT:    .cfi_def_cfa_offset 32
; V83A-NEXT:    mov w8, #1 // =0x1
; V83A-NEXT:    mov w9, #2 // =0x2
; V83A-NEXT:    stp w9, w8, [sp, #24]
; V83A-NEXT:    mov w9, #3 // =0x3
; V83A-NEXT:    mov w8, #4 // =0x4
; V83A-NEXT:    stp w8, w9, [sp, #16]
; V83A-NEXT:    mov w9, #5 // =0x5
; V83A-NEXT:    mov w8, #6 // =0x6
; V83A-NEXT:    stp w8, w9, [sp, #8]
; V83A-NEXT:    add sp, sp, #32
; V83A-NEXT:    retaa
  %1 = alloca i32, align 4
  %2 = alloca i32, align 4
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  store i32 1, ptr %1, align 4
  store i32 2, ptr %2, align 4
  store i32 3, ptr %3, align 4
  store i32 4, ptr %4, align 4
  store i32 5, ptr %5, align 4
  store i32 6, ptr %6, align 4
  ret void
}

; CHECK-NOT:      OUTLINED_FUNCTION_0:
; CHECK-NOT:      // -- Begin function
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; CHECK: {{.*}}