| // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --check-attributes --check-globals --include-generated-funcs --global-value-regex ".*" |
| // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -emit-llvm -o - %s | FileCheck %s |
| // RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature -fmv -emit-llvm -o - %s | FileCheck %s -check-prefix=CHECK-NOFMV |
| |
| int __attribute__((target_version("rng+flagm+fp16fml"))) fmv(void) { return 1; } |
| int __attribute__((target_version("flagm2+sme-i16i64"))) fmv(void) { return 2; } |
| int __attribute__((target_version("lse+sha2"))) fmv(void) { return 3; } |
| int __attribute__((target_version("dotprod+wfxt"))) fmv(void) { return 4; } |
| int __attribute__((target_version("fp16fml+memtag"))) fmv(void) { return 5; } |
| int __attribute__((target_version("fp+aes"))) fmv(void) { return 6; } |
| int __attribute__((target_version("crc+wfxt"))) fmv(void) { return 7; } |
| int __attribute__((target_version("bti"))) fmv(void) { return 8; } |
| int __attribute__((target_version("sme2"))) fmv(void) { return 9; } |
| int __attribute__((target_version("default"))) fmv(void) { return 0; } |
| int __attribute__((target_version("wfxt+simd"))) fmv_one(void) { return 1; } |
| int __attribute__((target_version("dpb"))) fmv_one(void) { return 2; } |
| int __attribute__((target_version("default"))) fmv_one(void) { return 0; } |
| int __attribute__((target_version("fp"))) fmv_two(void) { return 1; } |
| int __attribute__((target_version("simd"))) fmv_two(void) { return 2; } |
| int __attribute__((target_version("fp16+simd"))) fmv_two(void) { return 4; } |
| int __attribute__((target_version("default"))) fmv_two(void) { return 0; } |
| int foo() { |
| return fmv()+fmv_one()+fmv_two(); |
| } |
| |
| inline int __attribute__((target_version("sha2+aes+f64mm"))) fmv_inline(void) { return 1; } |
| inline int __attribute__((target_version("fp16+fcma+rdma+sme+ fp16 "))) fmv_inline(void) { return 2; } |
| inline int __attribute__((target_version("sha3+i8mm+f32mm"))) fmv_inline(void) { return 12; } |
| inline int __attribute__((target_version("dit+bf16"))) fmv_inline(void) { return 8; } |
| inline int __attribute__((target_version("dpb+rcpc2 "))) fmv_inline(void) { return 6; } |
| inline int __attribute__((target_version(" dpb2 + jscvt"))) fmv_inline(void) { return 7; } |
| inline int __attribute__((target_version("rcpc+frintts"))) fmv_inline(void) { return 3; } |
| inline int __attribute__((target_version("sve+bf16"))) fmv_inline(void) { return 4; } |
| inline int __attribute__((target_version("sve2-aes+sve2-sha3"))) fmv_inline(void) { return 5; } |
| inline int __attribute__((target_version("sve2+sve2-aes+sve2-bitperm"))) fmv_inline(void) { return 9; } |
| inline int __attribute__((target_version("sve2-sm4+memtag"))) fmv_inline(void) { return 10; } |
| inline int __attribute__((target_version("memtag+rcpc3+mops"))) fmv_inline(void) { return 11; } |
| inline int __attribute__((target_version("aes+dotprod"))) fmv_inline(void) { return 13; } |
| inline int __attribute__((target_version("simd+fp16fml"))) fmv_inline(void) { return 14; } |
| inline int __attribute__((target_version("fp+sm4"))) fmv_inline(void) { return 15; } |
| inline int __attribute__((target_version("lse+rdm"))) fmv_inline(void) { return 16; } |
| inline int __attribute__((target_version("default"))) fmv_inline(void) { return 3; } |
| |
| __attribute__((target_version("wfxt"))) int fmv_e(void); |
| int fmv_e(void) { return 20; } |
| |
| static __attribute__((target_version("sb"))) inline int fmv_d(void); |
| static __attribute__((target_version("default"))) inline int fmv_d(void); |
| |
| int __attribute__((target_version("default"))) fmv_default(void) { return 111; } |
| int fmv_default(void); |
| |
| void fmv_c(void); |
| void __attribute__((target_version("ssbs"))) fmv_c(void){}; |
| void __attribute__((target_version("default"))) fmv_c(void){}; |
| |
| int goo() { |
| fmv_inline(); |
| fmv_e(); |
| fmv_d(); |
| fmv_c(); |
| return fmv_default(); |
| } |
| static inline int __attribute__((target_version("sb"))) fmv_d(void) { return 0; } |
| static inline int __attribute__((target_version(" default "))) fmv_d(void) { return 1; } |
| |
| static void func(void) {} |
| inline __attribute__((target_version("default"))) void recb(void) { func(); } |
| inline __attribute__((target_version("default"))) void reca(void) { recb(); } |
| void recur(void) { reca(); } |
| |
| int __attribute__((target_version("default"))) main(void) { |
| recur(); |
| return goo(); |
| } |
| |
| typedef int (*Fptr)(); |
| void f(Fptr); |
| int hoo(void) { |
| f(fmv); |
| Fptr fp1 = &fmv; |
| Fptr fp2 = fmv; |
| return fp1() + fp2(); |
| } |
| |
| // This should generate one target version but no resolver. |
| __attribute__((target_version("default"))) int unused_with_forward_default_decl(void); |
| __attribute__((target_version("mops"))) int unused_with_forward_default_decl(void) { return 0; } |
| |
| // This should also generate one target version but no resolver. |
| extern int unused_with_implicit_extern_forward_default_decl(void); |
| __attribute__((target_version("dotprod"))) |
| int unused_with_implicit_extern_forward_default_decl(void) { return 0; } |
| |
| // This should also generate one target version but no resolver. |
| __attribute__((target_version("aes"))) int unused_with_default_decl(void) { return 0; } |
| __attribute__((target_version("default"))) int unused_with_default_decl(void); |
| |
| // This should generate two target versions and the resolver. |
| __attribute__((target_version("sve"))) int unused_with_default_def(void) { return 0; } |
| __attribute__((target_version("default"))) int unused_with_default_def(void) { return 1; } |
| |
| // This should also generate two target versions and the resolver. |
| __attribute__((target_version("fp16"))) int unused_with_implicit_default_def(void) { return 0; } |
| int unused_with_implicit_default_def(void) { return 1; } |
| |
| // This should also generate two target versions and the resolver. |
| int unused_with_implicit_forward_default_def(void) { return 0; } |
| __attribute__((target_version("lse"))) int unused_with_implicit_forward_default_def(void) { return 1; } |
| |
| // This should generate a target version despite the default not being declared. |
| __attribute__((target_version("rdm"))) int unused_without_default(void) { return 0; } |
| |
| // These shouldn't generate anything. |
| int unused_version_declarations(void); |
| __attribute__((target_version("jscvt"))) int unused_version_declarations(void); |
| __attribute__((target_version("rdma"))) int unused_version_declarations(void); |
| |
| // These should generate the default (mangled) version and the resolver. |
| int default_def_with_version_decls(void) { return 0; } |
| __attribute__((target_version("jscvt"))) int default_def_with_version_decls(void); |
| __attribute__((target_version("rdma"))) int default_def_with_version_decls(void); |
| |
| // The following is guarded because in NOFMV we get errors for calling undeclared functions. |
| #ifdef __HAVE_FUNCTION_MULTI_VERSIONING |
| // This should generate a default declaration, two target versions but no resolver. |
| __attribute__((target_version("jscvt"))) int used_def_without_default_decl(void) { return 1; } |
| __attribute__((target_version("rdma"))) int used_def_without_default_decl(void) { return 2; } |
| |
| // This should generate a default declaration but no resolver. |
| __attribute__((target_version("jscvt"))) int used_decl_without_default_decl(void); |
| __attribute__((target_version("rdma"))) int used_decl_without_default_decl(void); |
| |
| int caller(void) { return used_def_without_default_decl() + used_decl_without_default_decl(); } |
| #endif |
| |
| //. |
| // CHECK: @__aarch64_cpu_features = external dso_local global { i64 } |
| // CHECK: @fmv = weak_odr ifunc i32 (), ptr @fmv.resolver |
| // CHECK: @fmv_one = weak_odr ifunc i32 (), ptr @fmv_one.resolver |
| // CHECK: @fmv_two = weak_odr ifunc i32 (), ptr @fmv_two.resolver |
| // CHECK: @fmv_e = weak_odr ifunc i32 (), ptr @fmv_e.resolver |
| // CHECK: @fmv_d = internal ifunc i32 (), ptr @fmv_d.resolver |
| // CHECK: @fmv_default = weak_odr ifunc i32 (), ptr @fmv_default.resolver |
| // CHECK: @fmv_c = weak_odr ifunc void (), ptr @fmv_c.resolver |
| // CHECK: @fmv_inline = weak_odr ifunc i32 (), ptr @fmv_inline.resolver |
| // CHECK: @reca = weak_odr ifunc void (), ptr @reca.resolver |
| // CHECK: @unused_with_default_def = weak_odr ifunc i32 (), ptr @unused_with_default_def.resolver |
| // CHECK: @unused_with_implicit_default_def = weak_odr ifunc i32 (), ptr @unused_with_implicit_default_def.resolver |
| // CHECK: @unused_with_implicit_forward_default_def = weak_odr ifunc i32 (), ptr @unused_with_implicit_forward_default_def.resolver |
| // CHECK: @default_def_with_version_decls = weak_odr ifunc i32 (), ptr @default_def_with_version_decls.resolver |
| // CHECK: @recb = weak_odr ifunc void (), ptr @recb.resolver |
| //. |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: define {{[^@]+}}@fmv._MflagmMfp16fmlMrng |
| // CHECK-SAME: () #[[ATTR0:[0-9]+]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 1 |
| // |
| // |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: define {{[^@]+}}@fmv._Mflagm2Msme-i16i64 |
| // CHECK-SAME: () #[[ATTR1:[0-9]+]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 2 |
| // |
| // |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: define {{[^@]+}}@fmv._MlseMsha2 |
| // CHECK-SAME: () #[[ATTR2:[0-9]+]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 3 |
| // |
| // |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: define {{[^@]+}}@fmv._MdotprodMwfxt |
| // CHECK-SAME: () #[[ATTR3:[0-9]+]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 4 |
| // |
| // |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: define {{[^@]+}}@fmv._Mfp16fmlMmemtag |
| // CHECK-SAME: () #[[ATTR4:[0-9]+]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 5 |
| // |
| // |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: define {{[^@]+}}@fmv._MaesMfp |
| // CHECK-SAME: () #[[ATTR5:[0-9]+]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 6 |
| // |
| // |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: define {{[^@]+}}@fmv._McrcMwfxt |
| // CHECK-SAME: () #[[ATTR6:[0-9]+]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 7 |
| // |
| // |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: define {{[^@]+}}@fmv._Mbti |
| // CHECK-SAME: () #[[ATTR7:[0-9]+]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 8 |
| // |
| // |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: define {{[^@]+}}@fmv._Msme2 |
| // CHECK-SAME: () #[[ATTR8:[0-9]+]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 9 |
| // |
| // |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: define {{[^@]+}}@fmv.default |
| // CHECK-SAME: () #[[ATTR9:[0-9]+]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 0 |
| // |
| // |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: define {{[^@]+}}@fmv_one._MsimdMwfxt |
| // CHECK-SAME: () #[[ATTR10:[0-9]+]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 1 |
| // |
| // |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: define {{[^@]+}}@fmv_one._Mdpb |
| // CHECK-SAME: () #[[ATTR11:[0-9]+]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 2 |
| // |
| // |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: define {{[^@]+}}@fmv_one.default |
| // CHECK-SAME: () #[[ATTR9]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 0 |
| // |
| // |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: define {{[^@]+}}@fmv_two._Mfp |
| // CHECK-SAME: () #[[ATTR12:[0-9]+]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 1 |
| // |
| // |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: define {{[^@]+}}@fmv_two._Msimd |
| // CHECK-SAME: () #[[ATTR13:[0-9]+]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 2 |
| // |
| // |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: define {{[^@]+}}@fmv_two._Mfp16Msimd |
| // CHECK-SAME: () #[[ATTR14:[0-9]+]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 4 |
| // |
| // |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: define {{[^@]+}}@fmv_two.default |
| // CHECK-SAME: () #[[ATTR9]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 0 |
| // |
| // |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: define {{[^@]+}}@foo |
| // CHECK-SAME: () #[[ATTR15:[0-9]+]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[CALL:%.*]] = call i32 @fmv() |
| // CHECK-NEXT: [[CALL1:%.*]] = call i32 @fmv_one() |
| // CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]] |
| // CHECK-NEXT: [[CALL2:%.*]] = call i32 @fmv_two() |
| // CHECK-NEXT: [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CALL2]] |
| // CHECK-NEXT: ret i32 [[ADD3]] |
| // |
| // |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: define {{[^@]+}}@fmv_e.default |
| // CHECK-SAME: () #[[ATTR9]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 20 |
| // |
| // |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: define {{[^@]+}}@fmv_default.default |
| // CHECK-SAME: () #[[ATTR9]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 111 |
| // |
| // |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: define {{[^@]+}}@fmv_c._Mssbs |
| // CHECK-SAME: () #[[ATTR16:[0-9]+]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret void |
| // |
| // |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: define {{[^@]+}}@fmv_c.default |
| // CHECK-SAME: () #[[ATTR9]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret void |
| // |
| // |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: define {{[^@]+}}@goo |
| // CHECK-SAME: () #[[ATTR15]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[CALL:%.*]] = call i32 @fmv_inline() |
| // CHECK-NEXT: [[CALL1:%.*]] = call i32 @fmv_e() |
| // CHECK-NEXT: [[CALL2:%.*]] = call i32 @fmv_d() |
| // CHECK-NEXT: call void @fmv_c() |
| // CHECK-NEXT: [[CALL3:%.*]] = call i32 @fmv_default() |
| // CHECK-NEXT: ret i32 [[CALL3]] |
| // |
| // |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: define {{[^@]+}}@recur |
| // CHECK-SAME: () #[[ATTR15]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: call void @reca() |
| // CHECK-NEXT: ret void |
| // |
| // |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: define {{[^@]+}}@hoo |
| // CHECK-SAME: () #[[ATTR15]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[FP1:%.*]] = alloca ptr, align 8 |
| // CHECK-NEXT: [[FP2:%.*]] = alloca ptr, align 8 |
| // CHECK-NEXT: call void @f(ptr noundef @fmv) |
| // CHECK-NEXT: store ptr @fmv, ptr [[FP1]], align 8 |
| // CHECK-NEXT: store ptr @fmv, ptr [[FP2]], align 8 |
| // CHECK-NEXT: [[TMP0:%.*]] = load ptr, ptr [[FP1]], align 8 |
| // CHECK-NEXT: [[CALL:%.*]] = call i32 [[TMP0]]() |
| // CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr [[FP2]], align 8 |
| // CHECK-NEXT: [[CALL1:%.*]] = call i32 [[TMP1]]() |
| // CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]] |
| // CHECK-NEXT: ret i32 [[ADD]] |
| // |
| // |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: define {{[^@]+}}@unused_with_forward_default_decl._Mmops |
| // CHECK-SAME: () #[[ATTR19:[0-9]+]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 0 |
| // |
| // |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: define {{[^@]+}}@unused_with_implicit_extern_forward_default_decl._Mdotprod |
| // CHECK-SAME: () #[[ATTR20:[0-9]+]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 0 |
| // |
| // |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: define {{[^@]+}}@unused_with_default_decl._Maes |
| // CHECK-SAME: () #[[ATTR21:[0-9]+]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 0 |
| // |
| // |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: define {{[^@]+}}@unused_with_default_def._Msve |
| // CHECK-SAME: () #[[ATTR22:[0-9]+]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 0 |
| // |
| // |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: define {{[^@]+}}@unused_with_default_def.default |
| // CHECK-SAME: () #[[ATTR9]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 1 |
| // |
| // |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: define {{[^@]+}}@unused_with_implicit_default_def._Mfp16 |
| // CHECK-SAME: () #[[ATTR23:[0-9]+]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 0 |
| // |
| // |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: define {{[^@]+}}@unused_with_implicit_default_def.default |
| // CHECK-SAME: () #[[ATTR9]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 1 |
| // |
| // |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: define {{[^@]+}}@unused_with_implicit_forward_default_def.default |
| // CHECK-SAME: () #[[ATTR15]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 0 |
| // |
| // |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: define {{[^@]+}}@unused_with_implicit_forward_default_def._Mlse |
| // CHECK-SAME: () #[[ATTR24:[0-9]+]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 1 |
| // |
| // |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: define {{[^@]+}}@unused_without_default._Mrdm |
| // CHECK-SAME: () #[[ATTR25:[0-9]+]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 0 |
| // |
| // |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: define {{[^@]+}}@default_def_with_version_decls.default |
| // CHECK-SAME: () #[[ATTR15]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 0 |
| // |
| // |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: define {{[^@]+}}@used_def_without_default_decl._Mjscvt |
| // CHECK-SAME: () #[[ATTR27:[0-9]+]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 1 |
| // |
| // |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: define {{[^@]+}}@used_def_without_default_decl._Mrdm |
| // CHECK-SAME: () #[[ATTR28:[0-9]+]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 2 |
| // |
| // |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: define {{[^@]+}}@caller |
| // CHECK-SAME: () #[[ATTR15]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[CALL:%.*]] = call i32 @used_def_without_default_decl() |
| // CHECK-NEXT: [[CALL1:%.*]] = call i32 @used_decl_without_default_decl() |
| // CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]] |
| // CHECK-NEXT: ret i32 [[ADD]] |
| // |
| // |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: define {{[^@]+}}@main |
| // CHECK-SAME: () #[[ATTR9]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 |
| // CHECK-NEXT: store i32 0, ptr [[RETVAL]], align 4 |
| // CHECK-NEXT: call void @recur() |
| // CHECK-NEXT: [[CALL:%.*]] = call i32 @goo() |
| // CHECK-NEXT: ret i32 [[CALL]] |
| // |
| // |
| // CHECK-LABEL: define {{[^@]+}}@fmv.resolver() comdat { |
| // CHECK-NEXT: resolver_entry: |
| // CHECK-NEXT: call void @__init_cpu_features_resolver() |
| // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 |
| // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 144119586256651008 |
| // CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 144119586256651008 |
| // CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] |
| // CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] |
| // CHECK: resolver_return: |
| // CHECK-NEXT: ret ptr @fmv._Msme2 |
| // CHECK: resolver_else: |
| // CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 |
| // CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 72061992218723078 |
| // CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 72061992218723078 |
| // CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]] |
| // CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] |
| // CHECK: resolver_return1: |
| // CHECK-NEXT: ret ptr @fmv._Mflagm2Msme-i16i64 |
| // CHECK: resolver_else2: |
| // CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 |
| // CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 18014398509483008 |
| // CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 18014398509483008 |
| // CHECK-NEXT: [[TMP11:%.*]] = and i1 true, [[TMP10]] |
| // CHECK-NEXT: br i1 [[TMP11]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]] |
| // CHECK: resolver_return3: |
| // CHECK-NEXT: ret ptr @fmv._McrcMwfxt |
| // CHECK: resolver_else4: |
| // CHECK-NEXT: [[TMP12:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 |
| // CHECK-NEXT: [[TMP13:%.*]] = and i64 [[TMP12]], 18014398509482768 |
| // CHECK-NEXT: [[TMP14:%.*]] = icmp eq i64 [[TMP13]], 18014398509482768 |
| // CHECK-NEXT: [[TMP15:%.*]] = and i1 true, [[TMP14]] |
| // CHECK-NEXT: br i1 [[TMP15]], label [[RESOLVER_RETURN5:%.*]], label [[RESOLVER_ELSE6:%.*]] |
| // CHECK: resolver_return5: |
| // CHECK-NEXT: ret ptr @fmv._MdotprodMwfxt |
| // CHECK: resolver_else6: |
| // CHECK-NEXT: [[TMP16:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 |
| // CHECK-NEXT: [[TMP17:%.*]] = and i64 [[TMP16]], 1125899906842624 |
| // CHECK-NEXT: [[TMP18:%.*]] = icmp eq i64 [[TMP17]], 1125899906842624 |
| // CHECK-NEXT: [[TMP19:%.*]] = and i1 true, [[TMP18]] |
| // CHECK-NEXT: br i1 [[TMP19]], label [[RESOLVER_RETURN7:%.*]], label [[RESOLVER_ELSE8:%.*]] |
| // CHECK: resolver_return7: |
| // CHECK-NEXT: ret ptr @fmv._Mbti |
| // CHECK: resolver_else8: |
| // CHECK-NEXT: [[TMP20:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 |
| // CHECK-NEXT: [[TMP21:%.*]] = and i64 [[TMP20]], 17592186110728 |
| // CHECK-NEXT: [[TMP22:%.*]] = icmp eq i64 [[TMP21]], 17592186110728 |
| // CHECK-NEXT: [[TMP23:%.*]] = and i1 true, [[TMP22]] |
| // CHECK-NEXT: br i1 [[TMP23]], label [[RESOLVER_RETURN9:%.*]], label [[RESOLVER_ELSE10:%.*]] |
| // CHECK: resolver_return9: |
| // CHECK-NEXT: ret ptr @fmv._Mfp16fmlMmemtag |
| // CHECK: resolver_else10: |
| // CHECK-NEXT: [[TMP24:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 |
| // CHECK-NEXT: [[TMP25:%.*]] = and i64 [[TMP24]], 66315 |
| // CHECK-NEXT: [[TMP26:%.*]] = icmp eq i64 [[TMP25]], 66315 |
| // CHECK-NEXT: [[TMP27:%.*]] = and i1 true, [[TMP26]] |
| // CHECK-NEXT: br i1 [[TMP27]], label [[RESOLVER_RETURN11:%.*]], label [[RESOLVER_ELSE12:%.*]] |
| // CHECK: resolver_return11: |
| // CHECK-NEXT: ret ptr @fmv._MflagmMfp16fmlMrng |
| // CHECK: resolver_else12: |
| // CHECK-NEXT: [[TMP28:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 |
| // CHECK-NEXT: [[TMP29:%.*]] = and i64 [[TMP28]], 33536 |
| // CHECK-NEXT: [[TMP30:%.*]] = icmp eq i64 [[TMP29]], 33536 |
| // CHECK-NEXT: [[TMP31:%.*]] = and i1 true, [[TMP30]] |
| // CHECK-NEXT: br i1 [[TMP31]], label [[RESOLVER_RETURN13:%.*]], label [[RESOLVER_ELSE14:%.*]] |
| // CHECK: resolver_return13: |
| // CHECK-NEXT: ret ptr @fmv._MaesMfp |
| // CHECK: resolver_else14: |
| // CHECK-NEXT: [[TMP32:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 |
| // CHECK-NEXT: [[TMP33:%.*]] = and i64 [[TMP32]], 4992 |
| // CHECK-NEXT: [[TMP34:%.*]] = icmp eq i64 [[TMP33]], 4992 |
| // CHECK-NEXT: [[TMP35:%.*]] = and i1 true, [[TMP34]] |
| // CHECK-NEXT: br i1 [[TMP35]], label [[RESOLVER_RETURN15:%.*]], label [[RESOLVER_ELSE16:%.*]] |
| // CHECK: resolver_return15: |
| // CHECK-NEXT: ret ptr @fmv._MlseMsha2 |
| // CHECK: resolver_else16: |
| // CHECK-NEXT: ret ptr @fmv.default |
| // |
| // |
| // CHECK-LABEL: define {{[^@]+}}@fmv_one.resolver() comdat { |
| // CHECK-NEXT: resolver_entry: |
| // CHECK-NEXT: call void @__init_cpu_features_resolver() |
| // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 |
| // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 18014398509482752 |
| // CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 18014398509482752 |
| // CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] |
| // CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] |
| // CHECK: resolver_return: |
| // CHECK-NEXT: ret ptr @fmv_one._MsimdMwfxt |
| // CHECK: resolver_else: |
| // CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 |
| // CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 262144 |
| // CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 262144 |
| // CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]] |
| // CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] |
| // CHECK: resolver_return1: |
| // CHECK-NEXT: ret ptr @fmv_one._Mdpb |
| // CHECK: resolver_else2: |
| // CHECK-NEXT: ret ptr @fmv_one.default |
| // |
| // |
| // CHECK-LABEL: define {{[^@]+}}@fmv_two.resolver() comdat { |
| // CHECK-NEXT: resolver_entry: |
| // CHECK-NEXT: call void @__init_cpu_features_resolver() |
| // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 |
| // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 66304 |
| // CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 66304 |
| // CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] |
| // CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] |
| // CHECK: resolver_return: |
| // CHECK-NEXT: ret ptr @fmv_two._Mfp16Msimd |
| // CHECK: resolver_else: |
| // CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 |
| // CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 768 |
| // CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 768 |
| // CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]] |
| // CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] |
| // CHECK: resolver_return1: |
| // CHECK-NEXT: ret ptr @fmv_two._Msimd |
| // CHECK: resolver_else2: |
| // CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 |
| // CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 256 |
| // CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 256 |
| // CHECK-NEXT: [[TMP11:%.*]] = and i1 true, [[TMP10]] |
| // CHECK-NEXT: br i1 [[TMP11]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]] |
| // CHECK: resolver_return3: |
| // CHECK-NEXT: ret ptr @fmv_two._Mfp |
| // CHECK: resolver_else4: |
| // CHECK-NEXT: ret ptr @fmv_two.default |
| // |
| // |
| // CHECK-LABEL: define {{[^@]+}}@fmv_e.resolver() comdat { |
| // CHECK-NEXT: resolver_entry: |
| // CHECK-NEXT: call void @__init_cpu_features_resolver() |
| // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 |
| // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 18014398509481984 |
| // CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 18014398509481984 |
| // CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] |
| // CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] |
| // CHECK: resolver_return: |
| // CHECK-NEXT: ret ptr @fmv_e._Mwfxt |
| // CHECK: resolver_else: |
| // CHECK-NEXT: ret ptr @fmv_e.default |
| // |
| // |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: define {{[^@]+}}@fmv_d._Msb |
| // CHECK-SAME: () #[[ATTR30:[0-9]+]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 0 |
| // |
| // |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: define {{[^@]+}}@fmv_d.default |
| // CHECK-SAME: () #[[ATTR9]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 1 |
| // |
| // |
| // CHECK-LABEL: define {{[^@]+}}@fmv_d.resolver() { |
| // CHECK-NEXT: resolver_entry: |
| // CHECK-NEXT: call void @__init_cpu_features_resolver() |
| // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 |
| // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 70368744177664 |
| // CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 70368744177664 |
| // CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] |
| // CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] |
| // CHECK: resolver_return: |
| // CHECK-NEXT: ret ptr @fmv_d._Msb |
| // CHECK: resolver_else: |
| // CHECK-NEXT: ret ptr @fmv_d.default |
| // |
| // |
| // CHECK-LABEL: define {{[^@]+}}@fmv_default.resolver() comdat { |
| // CHECK-NEXT: resolver_entry: |
| // CHECK-NEXT: ret ptr @fmv_default.default |
| // |
| // |
| // CHECK-LABEL: define {{[^@]+}}@fmv_c.resolver() comdat { |
| // CHECK-NEXT: resolver_entry: |
| // CHECK-NEXT: call void @__init_cpu_features_resolver() |
| // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 |
| // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 562949953421312 |
| // CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 562949953421312 |
| // CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] |
| // CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] |
| // CHECK: resolver_return: |
| // CHECK-NEXT: ret ptr @fmv_c._Mssbs |
| // CHECK: resolver_else: |
| // CHECK-NEXT: ret ptr @fmv_c.default |
| // |
| // |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: define {{[^@]+}}@fmv_inline._MaesMf64mmMsha2 |
| // CHECK-SAME: () #[[ATTR31:[0-9]+]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 1 |
| // |
| // |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: define {{[^@]+}}@fmv_inline._MfcmaMfp16MrdmMsme |
| // CHECK-SAME: () #[[ATTR32:[0-9]+]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 2 |
| // |
| // |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mf32mmMi8mmMsha3 |
| // CHECK-SAME: () #[[ATTR33:[0-9]+]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 12 |
| // |
| // |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mbf16Mdit |
| // CHECK-SAME: () #[[ATTR34:[0-9]+]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 8 |
| // |
| // |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: define {{[^@]+}}@fmv_inline._MdpbMrcpc2 |
| // CHECK-SAME: () #[[ATTR35:[0-9]+]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 6 |
| // |
| // |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mdpb2Mjscvt |
| // CHECK-SAME: () #[[ATTR36:[0-9]+]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 7 |
| // |
| // |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: define {{[^@]+}}@fmv_inline._MfrinttsMrcpc |
| // CHECK-SAME: () #[[ATTR37:[0-9]+]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 3 |
| // |
| // |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mbf16Msve |
| // CHECK-SAME: () #[[ATTR38:[0-9]+]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 4 |
| // |
| // |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: define {{[^@]+}}@fmv_inline._Msve2-aesMsve2-sha3 |
| // CHECK-SAME: () #[[ATTR39:[0-9]+]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 5 |
| // |
| // |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: define {{[^@]+}}@fmv_inline._Msve2Msve2-aesMsve2-bitperm |
| // CHECK-SAME: () #[[ATTR40:[0-9]+]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 9 |
| // |
| // |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: define {{[^@]+}}@fmv_inline._MmemtagMsve2-sm4 |
| // CHECK-SAME: () #[[ATTR41:[0-9]+]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 10 |
| // |
| // |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: define {{[^@]+}}@fmv_inline._MmemtagMmopsMrcpc3 |
| // CHECK-SAME: () #[[ATTR42:[0-9]+]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 11 |
| // |
| // |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: define {{[^@]+}}@fmv_inline._MaesMdotprod |
| // CHECK-SAME: () #[[ATTR43:[0-9]+]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 13 |
| // |
| // |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: define {{[^@]+}}@fmv_inline._Mfp16fmlMsimd |
| // CHECK-SAME: () #[[ATTR44:[0-9]+]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 14 |
| // |
| // |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: define {{[^@]+}}@fmv_inline._MfpMsm4 |
| // CHECK-SAME: () #[[ATTR45:[0-9]+]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 15 |
| // |
| // |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: define {{[^@]+}}@fmv_inline._MlseMrdm |
| // CHECK-SAME: () #[[ATTR46:[0-9]+]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 16 |
| // |
| // |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: define {{[^@]+}}@fmv_inline.default |
| // CHECK-SAME: () #[[ATTR9]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret i32 3 |
| // |
| // |
| // CHECK-LABEL: define {{[^@]+}}@fmv_inline.resolver() comdat { |
| // CHECK-NEXT: resolver_entry: |
| // CHECK-NEXT: call void @__init_cpu_features_resolver() |
| // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 |
| // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 864708720653762560 |
| // CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 864708720653762560 |
| // CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] |
| // CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] |
| // CHECK: resolver_return: |
| // CHECK-NEXT: ret ptr @fmv_inline._MmemtagMmopsMrcpc3 |
| // CHECK: resolver_else: |
| // CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 |
| // CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 19861002584864 |
| // CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 19861002584864 |
| // CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]] |
| // CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] |
| // CHECK: resolver_return1: |
| // CHECK-NEXT: ret ptr @fmv_inline._MmemtagMsve2-sm4 |
| // CHECK: resolver_else2: |
| // CHECK-NEXT: [[TMP8:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 |
| // CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], 4398182892352 |
| // CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[TMP9]], 4398182892352 |
| // CHECK-NEXT: [[TMP11:%.*]] = and i1 true, [[TMP10]] |
| // CHECK-NEXT: br i1 [[TMP11]], label [[RESOLVER_RETURN3:%.*]], label [[RESOLVER_ELSE4:%.*]] |
| // CHECK: resolver_return3: |
| // CHECK-NEXT: ret ptr @fmv_inline._MfcmaMfp16MrdmMsme |
| // CHECK: resolver_else4: |
| // CHECK-NEXT: [[TMP12:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 |
| // CHECK-NEXT: [[TMP13:%.*]] = and i64 [[TMP12]], 1444182864640 |
| // CHECK-NEXT: [[TMP14:%.*]] = icmp eq i64 [[TMP13]], 1444182864640 |
| // CHECK-NEXT: [[TMP15:%.*]] = and i1 true, [[TMP14]] |
| // CHECK-NEXT: br i1 [[TMP15]], label [[RESOLVER_RETURN5:%.*]], label [[RESOLVER_ELSE6:%.*]] |
| // CHECK: resolver_return5: |
| // CHECK-NEXT: ret ptr @fmv_inline._Msve2-aesMsve2-sha3 |
| // CHECK: resolver_else6: |
| // CHECK-NEXT: [[TMP16:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 |
| // CHECK-NEXT: [[TMP17:%.*]] = and i64 [[TMP16]], 894427038464 |
| // CHECK-NEXT: [[TMP18:%.*]] = icmp eq i64 [[TMP17]], 894427038464 |
| // CHECK-NEXT: [[TMP19:%.*]] = and i1 true, [[TMP18]] |
| // CHECK-NEXT: br i1 [[TMP19]], label [[RESOLVER_RETURN7:%.*]], label [[RESOLVER_ELSE8:%.*]] |
| // CHECK: resolver_return7: |
| // CHECK-NEXT: ret ptr @fmv_inline._Msve2Msve2-aesMsve2-bitperm |
| // CHECK: resolver_else8: |
| // CHECK-NEXT: [[TMP20:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 |
| // CHECK-NEXT: [[TMP21:%.*]] = and i64 [[TMP20]], 35433583360 |
| // CHECK-NEXT: [[TMP22:%.*]] = icmp eq i64 [[TMP21]], 35433583360 |
| // CHECK-NEXT: [[TMP23:%.*]] = and i1 true, [[TMP22]] |
| // CHECK-NEXT: br i1 [[TMP23]], label [[RESOLVER_RETURN9:%.*]], label [[RESOLVER_ELSE10:%.*]] |
| // CHECK: resolver_return9: |
| // CHECK-NEXT: ret ptr @fmv_inline._MaesMf64mmMsha2 |
| // CHECK: resolver_else10: |
| // CHECK-NEXT: [[TMP24:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 |
| // CHECK-NEXT: [[TMP25:%.*]] = and i64 [[TMP24]], 18320798464 |
| // CHECK-NEXT: [[TMP26:%.*]] = icmp eq i64 [[TMP25]], 18320798464 |
| // CHECK-NEXT: [[TMP27:%.*]] = and i1 true, [[TMP26]] |
| // CHECK-NEXT: br i1 [[TMP27]], label [[RESOLVER_RETURN11:%.*]], label [[RESOLVER_ELSE12:%.*]] |
| // CHECK: resolver_return11: |
| // CHECK-NEXT: ret ptr @fmv_inline._Mf32mmMi8mmMsha3 |
| // CHECK: resolver_else12: |
| // CHECK-NEXT: [[TMP28:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 |
| // CHECK-NEXT: [[TMP29:%.*]] = and i64 [[TMP28]], 1208025856 |
| // CHECK-NEXT: [[TMP30:%.*]] = icmp eq i64 [[TMP29]], 1208025856 |
| // CHECK-NEXT: [[TMP31:%.*]] = and i1 true, [[TMP30]] |
| // CHECK-NEXT: br i1 [[TMP31]], label [[RESOLVER_RETURN13:%.*]], label [[RESOLVER_ELSE14:%.*]] |
| // CHECK: resolver_return13: |
| // CHECK-NEXT: ret ptr @fmv_inline._Mbf16Msve |
| // CHECK: resolver_else14: |
| // CHECK-NEXT: [[TMP32:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 |
| // CHECK-NEXT: [[TMP33:%.*]] = and i64 [[TMP32]], 134349568 |
| // CHECK-NEXT: [[TMP34:%.*]] = icmp eq i64 [[TMP33]], 134349568 |
| // CHECK-NEXT: [[TMP35:%.*]] = and i1 true, [[TMP34]] |
| // CHECK-NEXT: br i1 [[TMP35]], label [[RESOLVER_RETURN15:%.*]], label [[RESOLVER_ELSE16:%.*]] |
| // CHECK: resolver_return15: |
| // CHECK-NEXT: ret ptr @fmv_inline._Mbf16Mdit |
| // CHECK: resolver_else16: |
| // CHECK-NEXT: [[TMP36:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 |
| // CHECK-NEXT: [[TMP37:%.*]] = and i64 [[TMP36]], 20971776 |
| // CHECK-NEXT: [[TMP38:%.*]] = icmp eq i64 [[TMP37]], 20971776 |
| // CHECK-NEXT: [[TMP39:%.*]] = and i1 true, [[TMP38]] |
| // CHECK-NEXT: br i1 [[TMP39]], label [[RESOLVER_RETURN17:%.*]], label [[RESOLVER_ELSE18:%.*]] |
| // CHECK: resolver_return17: |
| // CHECK-NEXT: ret ptr @fmv_inline._MfrinttsMrcpc |
| // CHECK: resolver_else18: |
| // CHECK-NEXT: [[TMP40:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 |
| // CHECK-NEXT: [[TMP41:%.*]] = and i64 [[TMP40]], 12845056 |
| // CHECK-NEXT: [[TMP42:%.*]] = icmp eq i64 [[TMP41]], 12845056 |
| // CHECK-NEXT: [[TMP43:%.*]] = and i1 true, [[TMP42]] |
| // CHECK-NEXT: br i1 [[TMP43]], label [[RESOLVER_RETURN19:%.*]], label [[RESOLVER_ELSE20:%.*]] |
| // CHECK: resolver_return19: |
| // CHECK-NEXT: ret ptr @fmv_inline._MdpbMrcpc2 |
| // CHECK: resolver_else20: |
| // CHECK-NEXT: [[TMP44:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 |
| // CHECK-NEXT: [[TMP45:%.*]] = and i64 [[TMP44]], 1835264 |
| // CHECK-NEXT: [[TMP46:%.*]] = icmp eq i64 [[TMP45]], 1835264 |
| // CHECK-NEXT: [[TMP47:%.*]] = and i1 true, [[TMP46]] |
| // CHECK-NEXT: br i1 [[TMP47]], label [[RESOLVER_RETURN21:%.*]], label [[RESOLVER_ELSE22:%.*]] |
| // CHECK: resolver_return21: |
| // CHECK-NEXT: ret ptr @fmv_inline._Mdpb2Mjscvt |
| // CHECK: resolver_else22: |
| // CHECK-NEXT: [[TMP48:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 |
| // CHECK-NEXT: [[TMP49:%.*]] = and i64 [[TMP48]], 66312 |
| // CHECK-NEXT: [[TMP50:%.*]] = icmp eq i64 [[TMP49]], 66312 |
| // CHECK-NEXT: [[TMP51:%.*]] = and i1 true, [[TMP50]] |
| // CHECK-NEXT: br i1 [[TMP51]], label [[RESOLVER_RETURN23:%.*]], label [[RESOLVER_ELSE24:%.*]] |
| // CHECK: resolver_return23: |
| // CHECK-NEXT: ret ptr @fmv_inline._Mfp16fmlMsimd |
| // CHECK: resolver_else24: |
| // CHECK-NEXT: [[TMP52:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 |
| // CHECK-NEXT: [[TMP53:%.*]] = and i64 [[TMP52]], 33552 |
| // CHECK-NEXT: [[TMP54:%.*]] = icmp eq i64 [[TMP53]], 33552 |
| // CHECK-NEXT: [[TMP55:%.*]] = and i1 true, [[TMP54]] |
| // CHECK-NEXT: br i1 [[TMP55]], label [[RESOLVER_RETURN25:%.*]], label [[RESOLVER_ELSE26:%.*]] |
| // CHECK: resolver_return25: |
| // CHECK-NEXT: ret ptr @fmv_inline._MaesMdotprod |
| // CHECK: resolver_else26: |
| // CHECK-NEXT: [[TMP56:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 |
| // CHECK-NEXT: [[TMP57:%.*]] = and i64 [[TMP56]], 960 |
| // CHECK-NEXT: [[TMP58:%.*]] = icmp eq i64 [[TMP57]], 960 |
| // CHECK-NEXT: [[TMP59:%.*]] = and i1 true, [[TMP58]] |
| // CHECK-NEXT: br i1 [[TMP59]], label [[RESOLVER_RETURN27:%.*]], label [[RESOLVER_ELSE28:%.*]] |
| // CHECK: resolver_return27: |
| // CHECK-NEXT: ret ptr @fmv_inline._MlseMrdm |
| // CHECK: resolver_else28: |
| // CHECK-NEXT: [[TMP60:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 |
| // CHECK-NEXT: [[TMP61:%.*]] = and i64 [[TMP60]], 800 |
| // CHECK-NEXT: [[TMP62:%.*]] = icmp eq i64 [[TMP61]], 800 |
| // CHECK-NEXT: [[TMP63:%.*]] = and i1 true, [[TMP62]] |
| // CHECK-NEXT: br i1 [[TMP63]], label [[RESOLVER_RETURN29:%.*]], label [[RESOLVER_ELSE30:%.*]] |
| // CHECK: resolver_return29: |
| // CHECK-NEXT: ret ptr @fmv_inline._MfpMsm4 |
| // CHECK: resolver_else30: |
| // CHECK-NEXT: ret ptr @fmv_inline.default |
| // |
| // |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: define {{[^@]+}}@reca.default |
| // CHECK-SAME: () #[[ATTR9]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: call void @recb() |
| // CHECK-NEXT: ret void |
| // |
| // |
| // CHECK-LABEL: define {{[^@]+}}@reca.resolver() comdat { |
| // CHECK-NEXT: resolver_entry: |
| // CHECK-NEXT: ret ptr @reca.default |
| // |
| // |
| // CHECK-LABEL: define {{[^@]+}}@unused_with_default_def.resolver() comdat { |
| // CHECK-NEXT: resolver_entry: |
| // CHECK-NEXT: call void @__init_cpu_features_resolver() |
| // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 |
| // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 1073807616 |
| // CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1073807616 |
| // CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] |
| // CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] |
| // CHECK: resolver_return: |
| // CHECK-NEXT: ret ptr @unused_with_default_def._Msve |
| // CHECK: resolver_else: |
| // CHECK-NEXT: ret ptr @unused_with_default_def.default |
| // |
| // |
| // CHECK-LABEL: define {{[^@]+}}@unused_with_implicit_default_def.resolver() comdat { |
| // CHECK-NEXT: resolver_entry: |
| // CHECK-NEXT: call void @__init_cpu_features_resolver() |
| // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 |
| // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 65792 |
| // CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 65792 |
| // CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] |
| // CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] |
| // CHECK: resolver_return: |
| // CHECK-NEXT: ret ptr @unused_with_implicit_default_def._Mfp16 |
| // CHECK: resolver_else: |
| // CHECK-NEXT: ret ptr @unused_with_implicit_default_def.default |
| // |
| // |
| // CHECK-LABEL: define {{[^@]+}}@unused_with_implicit_forward_default_def.resolver() comdat { |
| // CHECK-NEXT: resolver_entry: |
| // CHECK-NEXT: call void @__init_cpu_features_resolver() |
| // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 |
| // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 128 |
| // CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 128 |
| // CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] |
| // CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] |
| // CHECK: resolver_return: |
| // CHECK-NEXT: ret ptr @unused_with_implicit_forward_default_def._Mlse |
| // CHECK: resolver_else: |
| // CHECK-NEXT: ret ptr @unused_with_implicit_forward_default_def.default |
| // |
| // |
| // CHECK-LABEL: define {{[^@]+}}@default_def_with_version_decls.resolver() comdat { |
| // CHECK-NEXT: resolver_entry: |
| // CHECK-NEXT: call void @__init_cpu_features_resolver() |
| // CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 |
| // CHECK-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 1048832 |
| // CHECK-NEXT: [[TMP2:%.*]] = icmp eq i64 [[TMP1]], 1048832 |
| // CHECK-NEXT: [[TMP3:%.*]] = and i1 true, [[TMP2]] |
| // CHECK-NEXT: br i1 [[TMP3]], label [[RESOLVER_RETURN:%.*]], label [[RESOLVER_ELSE:%.*]] |
| // CHECK: resolver_return: |
| // CHECK-NEXT: ret ptr @default_def_with_version_decls._Mjscvt |
| // CHECK: resolver_else: |
| // CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr @__aarch64_cpu_features, align 8 |
| // CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], 832 |
| // CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[TMP5]], 832 |
| // CHECK-NEXT: [[TMP7:%.*]] = and i1 true, [[TMP6]] |
| // CHECK-NEXT: br i1 [[TMP7]], label [[RESOLVER_RETURN1:%.*]], label [[RESOLVER_ELSE2:%.*]] |
| // CHECK: resolver_return1: |
| // CHECK-NEXT: ret ptr @default_def_with_version_decls._Mrdm |
| // CHECK: resolver_else2: |
| // CHECK-NEXT: ret ptr @default_def_with_version_decls.default |
| // |
| // |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: define {{[^@]+}}@recb.default |
| // CHECK-SAME: () #[[ATTR9]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: call void @func() |
| // CHECK-NEXT: ret void |
| // |
| // |
| // CHECK: Function Attrs: noinline nounwind optnone |
| // CHECK-LABEL: define {{[^@]+}}@func |
| // CHECK-SAME: () #[[ATTR15]] { |
| // CHECK-NEXT: entry: |
| // CHECK-NEXT: ret void |
| // |
| // |
| // CHECK-LABEL: define {{[^@]+}}@recb.resolver() comdat { |
| // CHECK-NEXT: resolver_entry: |
| // CHECK-NEXT: ret ptr @recb.default |
| // |
| // |
| // CHECK-NOFMV: Function Attrs: noinline nounwind optnone |
| // CHECK-NOFMV-LABEL: define {{[^@]+}}@foo |
| // CHECK-NOFMV-SAME: () #[[ATTR0:[0-9]+]] { |
| // CHECK-NOFMV-NEXT: entry: |
| // CHECK-NOFMV-NEXT: [[CALL:%.*]] = call i32 @fmv() |
| // CHECK-NOFMV-NEXT: [[CALL1:%.*]] = call i32 @fmv_one() |
| // CHECK-NOFMV-NEXT: [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]] |
| // CHECK-NOFMV-NEXT: [[CALL2:%.*]] = call i32 @fmv_two() |
| // CHECK-NOFMV-NEXT: [[ADD3:%.*]] = add nsw i32 [[ADD]], [[CALL2]] |
| // CHECK-NOFMV-NEXT: ret i32 [[ADD3]] |
| // |
| // |
| // CHECK-NOFMV: Function Attrs: noinline nounwind optnone |
| // CHECK-NOFMV-LABEL: define {{[^@]+}}@fmv |
| // CHECK-NOFMV-SAME: () #[[ATTR1:[0-9]+]] { |
| // CHECK-NOFMV-NEXT: entry: |
| // CHECK-NOFMV-NEXT: ret i32 0 |
| // |
| // |
| // CHECK-NOFMV: Function Attrs: noinline nounwind optnone |
| // CHECK-NOFMV-LABEL: define {{[^@]+}}@fmv_one |
| // CHECK-NOFMV-SAME: () #[[ATTR1]] { |
| // CHECK-NOFMV-NEXT: entry: |
| // CHECK-NOFMV-NEXT: ret i32 0 |
| // |
| // |
| // CHECK-NOFMV: Function Attrs: noinline nounwind optnone |
| // CHECK-NOFMV-LABEL: define {{[^@]+}}@fmv_two |
| // CHECK-NOFMV-SAME: () #[[ATTR1]] { |
| // CHECK-NOFMV-NEXT: entry: |
| // CHECK-NOFMV-NEXT: ret i32 0 |
| // |
| // |
| // CHECK-NOFMV: Function Attrs: noinline nounwind optnone |
| // CHECK-NOFMV-LABEL: define {{[^@]+}}@fmv_e |
| // CHECK-NOFMV-SAME: () #[[ATTR0]] { |
| // CHECK-NOFMV-NEXT: entry: |
| // CHECK-NOFMV-NEXT: ret i32 20 |
| // |
| // |
| // CHECK-NOFMV: Function Attrs: noinline nounwind optnone |
| // CHECK-NOFMV-LABEL: define {{[^@]+}}@goo |
| // CHECK-NOFMV-SAME: () #[[ATTR0]] { |
| // CHECK-NOFMV-NEXT: entry: |
| // CHECK-NOFMV-NEXT: [[CALL:%.*]] = call i32 @fmv_inline() |
| // CHECK-NOFMV-NEXT: [[CALL1:%.*]] = call i32 @fmv_e() |
| // CHECK-NOFMV-NEXT: [[CALL2:%.*]] = call i32 @fmv_d() |
| // CHECK-NOFMV-NEXT: call void @fmv_c() |
| // CHECK-NOFMV-NEXT: [[CALL3:%.*]] = call i32 @fmv_default() |
| // CHECK-NOFMV-NEXT: ret i32 [[CALL3]] |
| // |
| // |
| // CHECK-NOFMV: Function Attrs: noinline nounwind optnone |
| // CHECK-NOFMV-LABEL: define {{[^@]+}}@fmv_d |
| // CHECK-NOFMV-SAME: () #[[ATTR1]] { |
| // CHECK-NOFMV-NEXT: entry: |
| // CHECK-NOFMV-NEXT: ret i32 1 |
| // |
| // |
| // CHECK-NOFMV: Function Attrs: noinline nounwind optnone |
| // CHECK-NOFMV-LABEL: define {{[^@]+}}@fmv_c |
| // CHECK-NOFMV-SAME: () #[[ATTR1]] { |
| // CHECK-NOFMV-NEXT: entry: |
| // CHECK-NOFMV-NEXT: ret void |
| // |
| // |
| // CHECK-NOFMV: Function Attrs: noinline nounwind optnone |
| // CHECK-NOFMV-LABEL: define {{[^@]+}}@fmv_default |
| // CHECK-NOFMV-SAME: () #[[ATTR1]] { |
| // CHECK-NOFMV-NEXT: entry: |
| // CHECK-NOFMV-NEXT: ret i32 111 |
| // |
| // |
| // CHECK-NOFMV: Function Attrs: noinline nounwind optnone |
| // CHECK-NOFMV-LABEL: define {{[^@]+}}@recur |
| // CHECK-NOFMV-SAME: () #[[ATTR0]] { |
| // CHECK-NOFMV-NEXT: entry: |
| // CHECK-NOFMV-NEXT: call void @reca() |
| // CHECK-NOFMV-NEXT: ret void |
| // |
| // |
| // CHECK-NOFMV: Function Attrs: noinline nounwind optnone |
| // CHECK-NOFMV-LABEL: define {{[^@]+}}@hoo |
| // CHECK-NOFMV-SAME: () #[[ATTR0]] { |
| // CHECK-NOFMV-NEXT: entry: |
| // CHECK-NOFMV-NEXT: [[FP1:%.*]] = alloca ptr, align 8 |
| // CHECK-NOFMV-NEXT: [[FP2:%.*]] = alloca ptr, align 8 |
| // CHECK-NOFMV-NEXT: call void @f(ptr noundef @fmv) |
| // CHECK-NOFMV-NEXT: store ptr @fmv, ptr [[FP1]], align 8 |
| // CHECK-NOFMV-NEXT: store ptr @fmv, ptr [[FP2]], align 8 |
| // CHECK-NOFMV-NEXT: [[TMP0:%.*]] = load ptr, ptr [[FP1]], align 8 |
| // CHECK-NOFMV-NEXT: [[CALL:%.*]] = call i32 [[TMP0]]() |
| // CHECK-NOFMV-NEXT: [[TMP1:%.*]] = load ptr, ptr [[FP2]], align 8 |
| // CHECK-NOFMV-NEXT: [[CALL1:%.*]] = call i32 [[TMP1]]() |
| // CHECK-NOFMV-NEXT: [[ADD:%.*]] = add nsw i32 [[CALL]], [[CALL1]] |
| // CHECK-NOFMV-NEXT: ret i32 [[ADD]] |
| // |
| // |
| // CHECK-NOFMV: Function Attrs: noinline nounwind optnone |
| // CHECK-NOFMV-LABEL: define {{[^@]+}}@unused_with_implicit_default_def |
| // CHECK-NOFMV-SAME: () #[[ATTR0]] { |
| // CHECK-NOFMV-NEXT: entry: |
| // CHECK-NOFMV-NEXT: ret i32 1 |
| // |
| // |
| // CHECK-NOFMV: Function Attrs: noinline nounwind optnone |
| // CHECK-NOFMV-LABEL: define {{[^@]+}}@unused_with_implicit_forward_default_def |
| // CHECK-NOFMV-SAME: () #[[ATTR0]] { |
| // CHECK-NOFMV-NEXT: entry: |
| // CHECK-NOFMV-NEXT: ret i32 0 |
| // |
| // |
| // CHECK-NOFMV: Function Attrs: noinline nounwind optnone |
| // CHECK-NOFMV-LABEL: define {{[^@]+}}@default_def_with_version_decls |
| // CHECK-NOFMV-SAME: () #[[ATTR0]] { |
| // CHECK-NOFMV-NEXT: entry: |
| // CHECK-NOFMV-NEXT: ret i32 0 |
| // |
| // |
| // CHECK-NOFMV: Function Attrs: noinline nounwind optnone |
| // CHECK-NOFMV-LABEL: define {{[^@]+}}@main |
| // CHECK-NOFMV-SAME: () #[[ATTR1]] { |
| // CHECK-NOFMV-NEXT: entry: |
| // CHECK-NOFMV-NEXT: [[RETVAL:%.*]] = alloca i32, align 4 |
| // CHECK-NOFMV-NEXT: store i32 0, ptr [[RETVAL]], align 4 |
| // CHECK-NOFMV-NEXT: call void @recur() |
| // CHECK-NOFMV-NEXT: [[CALL:%.*]] = call i32 @goo() |
| // CHECK-NOFMV-NEXT: ret i32 [[CALL]] |
| // |
| // |
| // CHECK-NOFMV: Function Attrs: noinline nounwind optnone |
| // CHECK-NOFMV-LABEL: define {{[^@]+}}@unused_with_default_def |
| // CHECK-NOFMV-SAME: () #[[ATTR1]] { |
| // CHECK-NOFMV-NEXT: entry: |
| // CHECK-NOFMV-NEXT: ret i32 1 |
| // |
| //. |
| // CHECK: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4} |
| // CHECK: [[META1:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"} |
| //. |
| // CHECK-NOFMV: [[META0:![0-9]+]] = !{i32 1, !"wchar_size", i32 4} |
| // CHECK-NOFMV: [[META1:![0-9]+]] = !{!"{{.*}}clang version {{.*}}"} |
| //. |
