llvm/test/CodeGen/RISCV/rvv/cross-block-cse.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc < %s -O3 -mtriple=riscv64 -mattr=+v | FileCheck %s

; The case below demonstrates cross block CSE of vector instructions with
; undefined passthru operands.
define void @foo(<vscale x 2 x i32> %x, <vscale x 2 x i32> %y, ptr %p1, ptr %p2, i1 zeroext %cond) {
; CHECK-LABEL: foo:
; CHECK:       # %bb.0:
; CHECK-NEXT:    vsetvli a3, zero, e32, m1, ta, ma
; CHECK-NEXT:    vadd.vv v8, v8, v9
; CHECK-NEXT:    vs1r.v v8, (a0)
; CHECK-NEXT:    bnez a2, .LBB0_2
; CHECK-NEXT:  # %bb.1: # %falsebb
; CHECK-NEXT:    vs1r.v v8, (a1)
; CHECK-NEXT:  .LBB0_2: # %mergebb
; CHECK-NEXT:    ret
  %a = add <vscale x 2 x i32> %x, %y
  store <vscale x 2 x i32> %a, ptr %p1
  br i1 %cond, label %mergebb, label %falsebb

falsebb:
  %b = add <vscale x 2 x i32> %x, %y
  store <vscale x 2 x i32> %b, ptr %p2
  br label %mergebb

mergebb:
  ret void
}