| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py |
| ; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s |
| |
| declare <8 x i32> @llvm.loongarch.lasx.xvpermi.w(<8 x i32>, <8 x i32>, i32) |
| |
| define <8 x i32> @lasx_xvpermi_w(<8 x i32> %va, <8 x i32> %vb) nounwind { |
| ; CHECK-LABEL: lasx_xvpermi_w: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: xvpermi.w $xr0, $xr1, 1 |
| ; CHECK-NEXT: ret |
| entry: |
| %res = call <8 x i32> @llvm.loongarch.lasx.xvpermi.w(<8 x i32> %va, <8 x i32> %vb, i32 1) |
| ret <8 x i32> %res |
| } |
| |
| declare <4 x i64> @llvm.loongarch.lasx.xvpermi.d(<4 x i64>, i32) |
| |
| define <4 x i64> @lasx_xvpermi_d(<4 x i64> %va) nounwind { |
| ; CHECK-LABEL: lasx_xvpermi_d: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: xvpermi.d $xr0, $xr0, 1 |
| ; CHECK-NEXT: ret |
| entry: |
| %res = call <4 x i64> @llvm.loongarch.lasx.xvpermi.d(<4 x i64> %va, i32 1) |
| ret <4 x i64> %res |
| } |
| |
| declare <32 x i8> @llvm.loongarch.lasx.xvpermi.q(<32 x i8>, <32 x i8>, i32) |
| |
| define <32 x i8> @lasx_xvpermi_q(<32 x i8> %va, <32 x i8> %vb) nounwind { |
| ; CHECK-LABEL: lasx_xvpermi_q: |
| ; CHECK: # %bb.0: # %entry |
| ; CHECK-NEXT: xvpermi.q $xr0, $xr1, 1 |
| ; CHECK-NEXT: ret |
| entry: |
| %res = call <32 x i8> @llvm.loongarch.lasx.xvpermi.q(<32 x i8> %va, <32 x i8> %vb, i32 1) |
| ret <32 x i8> %res |
| } |