llvm/test/CodeGen/VE/Vector/storevr.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=ve-unknown-unknown -mattr=+vpu | FileCheck %s

@v256i64 = common dso_local local_unnamed_addr global <256 x i64> zeroinitializer, align 16

; Function Attrs: norecurse nounwind readonly
define fastcc void @storev256i64(ptr nocapture, <256 x i64>) {
; CHECK-LABEL: storev256i64:
; CHECK:       # %bb.0:
; CHECK-NEXT:    lea %s1, 256
; CHECK-NEXT:    lvl %s1
; CHECK-NEXT:    vst %v0, 8, %s0
; CHECK-NEXT:    b.l.t (, %s10)
  store <256 x i64> %1, ptr %0, align 16
  ret void
}

; Function Attrs: norecurse nounwind readonly
define fastcc void @storev256i64stk(<256 x i64>) {
; CHECK-LABEL: storev256i64stk:
; CHECK:       # %bb.0:
; CHECK-NEXT:    lea %s11, -2048(, %s11)
; CHECK-NEXT:    brge.l.t %s11, %s8, .LBB1_2
; CHECK-NEXT:  # %bb.1:
; CHECK-NEXT:    ld %s61, 24(, %s14)
; CHECK-NEXT:    or %s62, 0, %s0
; CHECK-NEXT:    lea %s63, 315
; CHECK-NEXT:    shm.l %s63, (%s61)
; CHECK-NEXT:    shm.l %s8, 8(%s61)
; CHECK-NEXT:    shm.l %s11, 16(%s61)
; CHECK-NEXT:    monc
; CHECK-NEXT:    or %s0, 0, %s62
; CHECK-NEXT:  .LBB1_2:
; CHECK-NEXT:    lea %s0, 256
; CHECK-NEXT:    lea %s1, (, %s11)
; CHECK-NEXT:    lvl %s0
; CHECK-NEXT:    vst %v0, 8, %s1
; CHECK-NEXT:    lea %s11, 2048(, %s11)
; CHECK-NEXT:    b.l.t (, %s10)
  %addr = alloca <256 x i64>, align 16
  store <256 x i64> %0, ptr %addr, align 16
  ret void
}

; Function Attrs: norecurse nounwind readonly
define fastcc void @storev256i64com(<256 x i64>) {
; CHECK-LABEL: storev256i64com:
; CHECK:       # %bb.0:
; CHECK-NEXT:    lea %s0, v256i64@lo
; CHECK-NEXT:    and %s0, %s0, (32)0
; CHECK-NEXT:    lea.sl %s0, v256i64@hi(, %s0)
; CHECK-NEXT:    lea %s1, 256
; CHECK-NEXT:    lvl %s1
; CHECK-NEXT:    vst %v0, 8, %s0
; CHECK-NEXT:    b.l.t (, %s10)
  store <256 x i64> %0, ptr @v256i64, align 16
  ret void
}