|  | //===---- RISCVISelDAGToDAG.h - A dag to dag inst selector for RISCV ------===// | 
|  | // | 
|  | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. | 
|  | // See https://llvm.org/LICENSE.txt for license information. | 
|  | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception | 
|  | // | 
|  | //===----------------------------------------------------------------------===// | 
|  | // | 
|  | // This file defines an instruction selector for the RISCV target. | 
|  | // | 
|  | //===----------------------------------------------------------------------===// | 
|  |  | 
|  | #ifndef LLVM_LIB_TARGET_RISCV_RISCVISELDAGTODAG_H | 
|  | #define LLVM_LIB_TARGET_RISCV_RISCVISELDAGTODAG_H | 
|  |  | 
|  | #include "RISCV.h" | 
|  | #include "RISCVTargetMachine.h" | 
|  | #include "llvm/CodeGen/SelectionDAGISel.h" | 
|  |  | 
|  | // RISCV-specific code to select RISCV machine instructions for | 
|  | // SelectionDAG operations. | 
|  | namespace llvm { | 
|  | class RISCVDAGToDAGISel : public SelectionDAGISel { | 
|  | const RISCVSubtarget *Subtarget = nullptr; | 
|  |  | 
|  | public: | 
|  | explicit RISCVDAGToDAGISel(RISCVTargetMachine &TargetMachine) | 
|  | : SelectionDAGISel(TargetMachine) {} | 
|  |  | 
|  | StringRef getPassName() const override { | 
|  | return "RISCV DAG->DAG Pattern Instruction Selection"; | 
|  | } | 
|  |  | 
|  | bool runOnMachineFunction(MachineFunction &MF) override { | 
|  | Subtarget = &MF.getSubtarget<RISCVSubtarget>(); | 
|  | return SelectionDAGISel::runOnMachineFunction(MF); | 
|  | } | 
|  |  | 
|  | void PostprocessISelDAG() override; | 
|  |  | 
|  | void Select(SDNode *Node) override; | 
|  |  | 
|  | bool SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID, | 
|  | std::vector<SDValue> &OutOps) override; | 
|  |  | 
|  | bool SelectAddrFI(SDValue Addr, SDValue &Base); | 
|  |  | 
|  | bool SelectSLOI(SDValue N, SDValue &RS1, SDValue &Shamt); | 
|  | bool SelectSROI(SDValue N, SDValue &RS1, SDValue &Shamt); | 
|  | bool SelectRORI(SDValue N, SDValue &RS1, SDValue &Shamt); | 
|  | bool SelectSLLIUW(SDValue N, SDValue &RS1, SDValue &Shamt); | 
|  | bool SelectSLOIW(SDValue N, SDValue &RS1, SDValue &Shamt); | 
|  | bool SelectSROIW(SDValue N, SDValue &RS1, SDValue &Shamt); | 
|  | bool SelectRORIW(SDValue N, SDValue &RS1, SDValue &Shamt); | 
|  | bool SelectFSRIW(SDValue N, SDValue &RS1, SDValue &RS2, SDValue &Shamt); | 
|  |  | 
|  | // Include the pieces autogenerated from the target description. | 
|  | #include "RISCVGenDAGISel.inc" | 
|  |  | 
|  | private: | 
|  | void doPeepholeLoadStoreADDI(); | 
|  | }; | 
|  | } | 
|  |  | 
|  | #endif |