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| <h1 id="hardware"><a class="header" href="#hardware">Hardware</a></h1> |
| <p>By now you should be somewhat familiar with the tooling and the development |
| process. In this section we’ll switch to real hardware; the process will remain |
| largely the same. Let’s dive in.</p> |
| <h2 id="know-your-hardware"><a class="header" href="#know-your-hardware">Know your hardware</a></h2> |
| <p>Before we begin you need to identify some characteristics of the target device |
| as these will be used to configure the project:</p> |
| <ul> |
| <li> |
| <p>The ARM core. e.g. Cortex-M3.</p> |
| </li> |
| <li> |
| <p>Does the ARM core include an FPU? Cortex-M4<strong>F</strong> and Cortex-M7<strong>F</strong> cores do.</p> |
| </li> |
| <li> |
| <p>How much Flash memory and RAM does the target device have? e.g. 256 KiB of |
| Flash and 32 KiB of RAM.</p> |
| </li> |
| <li> |
| <p>Where are Flash memory and RAM mapped in the address space? e.g. RAM is |
| commonly located at address <code>0x2000_0000</code>.</p> |
| </li> |
| </ul> |
| <p>You can find this information in the data sheet or the reference manual of your |
| device.</p> |
| <p>In this section we’ll be using our reference hardware, the STM32F3DISCOVERY. |
| This board contains an STM32F303VCT6 microcontroller. This microcontroller has:</p> |
| <ul> |
| <li> |
| <p>A Cortex-M4F core that includes a single precision FPU</p> |
| </li> |
| <li> |
| <p>256 KiB of Flash located at address 0x0800_0000.</p> |
| </li> |
| <li> |
| <p>40 KiB of RAM located at address 0x2000_0000. (There’s another RAM region but |
| for simplicity we’ll ignore it).</p> |
| </li> |
| </ul> |
| <h2 id="configuring"><a class="header" href="#configuring">Configuring</a></h2> |
| <p>We’ll start from scratch with a fresh template instance. Refer to the |
| <a href="qemu.html">previous section on QEMU</a> for a refresher on how to do this without |
| <code>cargo-generate</code>.</p> |
| <pre><code class="language-text">$ cargo generate --git https://github.com/rust-embedded/cortex-m-quickstart |
| Project Name: app |
| Creating project called `app`... |
| Done! New project created /tmp/app |
| |
| $ cd app |
| </code></pre> |
| <p>Step number one is to set a default compilation target in <code>.cargo/config.toml</code>.</p> |
| <pre><code class="language-console">tail -n5 .cargo/config.toml |
| </code></pre> |
| <pre><code class="language-toml"># Pick ONE of these compilation targets |
| # target = "thumbv6m-none-eabi" # Cortex-M0 and Cortex-M0+ |
| # target = "thumbv7m-none-eabi" # Cortex-M3 |
| # target = "thumbv7em-none-eabi" # Cortex-M4 and Cortex-M7 (no FPU) |
| target = "thumbv7em-none-eabihf" # Cortex-M4F and Cortex-M7F (with FPU) |
| </code></pre> |
| <p>We’ll use <code>thumbv7em-none-eabihf</code> as that covers the Cortex-M4F core.</p> |
| <blockquote> |
| <p><strong>NOTE</strong>: As you may remember from the previous chapter, we have to install |
| all targets and this is a new one. So don’t forget to run the installation |
| process <code>rustup target add thumbv7em-none-eabihf</code> for this target.</p> |
| </blockquote> |
| <p>The second step is to enter the memory region information into the <code>memory.x</code> |
| file.</p> |
| <pre><code class="language-text">$ cat memory.x |
| /* Linker script for the STM32F303VCT6 */ |
| MEMORY |
| { |
| /* NOTE 1 K = 1 KiBi = 1024 bytes */ |
| FLASH : ORIGIN = 0x08000000, LENGTH = 256K |
| RAM : ORIGIN = 0x20000000, LENGTH = 40K |
| } |
| </code></pre> |
| <blockquote> |
| <p><strong>NOTE</strong>: If you for some reason changed the <code>memory.x</code> file after you had made |
| the first build of a specific build target, then do <code>cargo clean</code> before |
| <code>cargo build</code>, because <code>cargo build</code> may not track updates of <code>memory.x</code>.</p> |
| </blockquote> |
| <p>We’ll start with the hello example again, but first we have to make a small |
| change.</p> |
| <p>In <code>examples/hello.rs</code>, make sure the <code>debug::exit()</code> call is commented out or |
| removed. It is used only for running in QEMU.</p> |
| <pre><code class="language-rust ignore">#[entry] |
| fn main() -> ! { |
| hprintln!("Hello, world!").unwrap(); |
| |
| // exit QEMU |
| // NOTE do not run this on hardware; it can corrupt OpenOCD state |
| // debug::exit(debug::EXIT_SUCCESS); |
| |
| loop {} |
| }</code></pre> |
| <p>You can now cross compile programs using <code>cargo build</code> |
| and inspect the binaries using <code>cargo-binutils</code> as you did before. The |
| <code>cortex-m-rt</code> crate handles all the magic required to get your chip running, |
| as helpfully, pretty much all Cortex-M CPUs boot in the same fashion.</p> |
| <pre><code class="language-console">cargo build --example hello |
| </code></pre> |
| <h2 id="debugging"><a class="header" href="#debugging">Debugging</a></h2> |
| <p>Debugging will look a bit different. In fact, the first steps can look different |
| depending on the target device. In this section we’ll show the steps required to |
| debug a program running on the STM32F3DISCOVERY. This is meant to serve as a |
| reference; for device specific information about debugging check out <a href="https://github.com/rust-embedded/debugonomicon">the |
| Debugonomicon</a>.</p> |
| <p>As before we’ll do remote debugging and the client will be a GDB process. This |
| time, however, the server will be OpenOCD.</p> |
| <p>As done during the <a href="../intro/install/verify.html">verify</a> section connect the discovery board to your laptop / |
| PC and check that the ST-LINK header is populated.</p> |
| <p>On a terminal run <code>openocd</code> to connect to the ST-LINK on the discovery board. |
| Run this command from the root of the template; <code>openocd</code> will pick up the |
| <code>openocd.cfg</code> file which indicates which interface file and target file to use.</p> |
| <pre><code class="language-console">cat openocd.cfg |
| </code></pre> |
| <pre><code class="language-text"># Sample OpenOCD configuration for the STM32F3DISCOVERY development board |
| |
| # Depending on the hardware revision you got you'll have to pick ONE of these |
| # interfaces. At any time only one interface should be commented out. |
| |
| # Revision C (newer revision) |
| source [find interface/stlink.cfg] |
| |
| # Revision A and B (older revisions) |
| # source [find interface/stlink-v2.cfg] |
| |
| source [find target/stm32f3x.cfg] |
| </code></pre> |
| <blockquote> |
| <p><strong>NOTE</strong> If you found out that you have an older revision of the discovery |
| board during the <a href="../intro/install/verify.html">verify</a> section then you should modify the <code>openocd.cfg</code> |
| file at this point to use <code>interface/stlink-v2.cfg</code>.</p> |
| </blockquote> |
| <pre><code class="language-text">$ openocd |
| Open On-Chip Debugger 0.10.0 |
| Licensed under GNU GPL v2 |
| For bug reports, read |
| http://openocd.org/doc/doxygen/bugs.html |
| Info : auto-selecting first available session transport "hla_swd". To override use 'transport select <transport>'. |
| adapter speed: 1000 kHz |
| adapter_nsrst_delay: 100 |
| Info : The selected transport took over low-level target control. The results might differ compared to plain JTAG/SWD |
| none separate |
| Info : Unable to match requested speed 1000 kHz, using 950 kHz |
| Info : Unable to match requested speed 1000 kHz, using 950 kHz |
| Info : clock speed 950 kHz |
| Info : STLINK v2 JTAG v27 API v2 SWIM v15 VID 0x0483 PID 0x374B |
| Info : using stlink api v2 |
| Info : Target voltage: 2.913879 |
| Info : stm32f3x.cpu: hardware has 6 breakpoints, 4 watchpoints |
| </code></pre> |
| <p>On another terminal run GDB, also from the root of the template.</p> |
| <pre><code class="language-text">gdb-multiarch -q target/thumbv7em-none-eabihf/debug/examples/hello |
| </code></pre> |
| <p><strong>NOTE</strong>: like before you might need another version of gdb instead of <code>gdb-multiarch</code> depending |
| on which one you installed in the installation chapter. This could also be |
| <code>arm-none-eabi-gdb</code> or just <code>gdb</code>.</p> |
| <p>Next connect GDB to OpenOCD, which is waiting for a TCP connection on port 3333.</p> |
| <pre><code class="language-console">(gdb) target remote :3333 |
| Remote debugging using :3333 |
| 0x00000000 in ?? () |
| </code></pre> |
| <p>Now proceed to <em>flash</em> (load) the program onto the microcontroller using the |
| <code>load</code> command.</p> |
| <pre><code class="language-console">(gdb) load |
| Loading section .vector_table, size 0x400 lma 0x8000000 |
| Loading section .text, size 0x1518 lma 0x8000400 |
| Loading section .rodata, size 0x414 lma 0x8001918 |
| Start address 0x08000400, load size 7468 |
| Transfer rate: 13 KB/sec, 2489 bytes/write. |
| </code></pre> |
| <p>The program is now loaded. This program uses semihosting so before we do any |
| semihosting call we have to tell OpenOCD to enable semihosting. You can send |
| commands to OpenOCD using the <code>monitor</code> command.</p> |
| <pre><code class="language-console">(gdb) monitor arm semihosting enable |
| semihosting is enabled |
| </code></pre> |
| <blockquote> |
| <p>You can see all the OpenOCD commands by invoking the <code>monitor help</code> command.</p> |
| </blockquote> |
| <p>Like before we can skip all the way to <code>main</code> using a breakpoint and the |
| <code>continue</code> command.</p> |
| <pre><code class="language-console">(gdb) break main |
| Breakpoint 1 at 0x8000490: file examples/hello.rs, line 11. |
| Note: automatically using hardware breakpoints for read-only addresses. |
| |
| (gdb) continue |
| Continuing. |
| |
| Breakpoint 1, hello::__cortex_m_rt_main_trampoline () at examples/hello.rs:11 |
| 11 #[entry] |
| </code></pre> |
| <blockquote> |
| <p><strong>NOTE</strong> If GDB blocks the terminal instead of hitting the breakpoint after |
| you issue the <code>continue</code> command above, you might want to double check that |
| the memory region information in the <code>memory.x</code> file is correctly set up |
| for your device (both the starts <em>and</em> lengths).</p> |
| </blockquote> |
| <p>Step into the main function with <code>step</code>.</p> |
| <pre><code class="language-console">(gdb) step |
| halted: PC: 0x08000496 |
| hello::__cortex_m_rt_main () at examples/hello.rs:13 |
| 13 hprintln!("Hello, world!").unwrap(); |
| </code></pre> |
| <p>After advancing the program with <code>next</code> you should see “Hello, world!” printed on the OpenOCD console, |
| among other stuff.</p> |
| <pre><code class="language-console">$ openocd |
| (..) |
| Info : halted: PC: 0x08000502 |
| Hello, world! |
| Info : halted: PC: 0x080004ac |
| Info : halted: PC: 0x080004ae |
| Info : halted: PC: 0x080004b0 |
| Info : halted: PC: 0x080004b4 |
| Info : halted: PC: 0x080004b8 |
| Info : halted: PC: 0x080004bc |
| </code></pre> |
| <p>The message is only displayed once as the program is about to enter the infinite loop defined in line 19: <code>loop {}</code></p> |
| <p>You can now exit GDB using the <code>quit</code> command.</p> |
| <pre><code class="language-console">(gdb) quit |
| A debugging session is active. |
| |
| Inferior 1 [Remote target] will be detached. |
| |
| Quit anyway? (y or n) |
| </code></pre> |
| <p>Debugging now requires a few more steps so we have packed all those steps into a |
| single GDB script named <code>openocd.gdb</code>. The file was created during the <code>cargo generate</code> step, and should work without any modifications. Let’s have a peek:</p> |
| <pre><code class="language-console">cat openocd.gdb |
| </code></pre> |
| <pre><code class="language-text">target extended-remote :3333 |
| |
| # print demangled symbols |
| set print asm-demangle on |
| |
| # detect unhandled exceptions, hard faults and panics |
| break DefaultHandler |
| break HardFault |
| break rust_begin_unwind |
| |
| monitor arm semihosting enable |
| |
| load |
| |
| # start the process but immediately halt the processor |
| stepi |
| </code></pre> |
| <p>Now running <code><gdb> -x openocd.gdb target/thumbv7em-none-eabihf/debug/examples/hello</code> will immediately connect GDB to |
| OpenOCD, enable semihosting, load the program and start the process.</p> |
| <p>Alternatively, you can turn <code><gdb> -x openocd.gdb</code> into a custom runner to make |
| <code>cargo run</code> build a program <em>and</em> start a GDB session. This runner is included |
| in <code>.cargo/config.toml</code> but it’s commented out.</p> |
| <pre><code class="language-console">head -n10 .cargo/config.toml |
| </code></pre> |
| <pre><code class="language-toml">[target.thumbv7m-none-eabi] |
| # uncomment this to make `cargo run` execute programs on QEMU |
| # runner = "qemu-system-arm -cpu cortex-m3 -machine lm3s6965evb -nographic -semihosting-config enable=on,target=native -kernel" |
| |
| [target.'cfg(all(target_arch = "arm", target_os = "none"))'] |
| # uncomment ONE of these three option to make `cargo run` start a GDB session |
| # which option to pick depends on your system |
| runner = "arm-none-eabi-gdb -x openocd.gdb" |
| # runner = "gdb-multiarch -x openocd.gdb" |
| # runner = "gdb -x openocd.gdb" |
| </code></pre> |
| <pre><code class="language-text">$ cargo run --example hello |
| (..) |
| Loading section .vector_table, size 0x400 lma 0x8000000 |
| Loading section .text, size 0x1e70 lma 0x8000400 |
| Loading section .rodata, size 0x61c lma 0x8002270 |
| Start address 0x800144e, load size 10380 |
| Transfer rate: 17 KB/sec, 3460 bytes/write. |
| (gdb) |
| </code></pre> |
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