llvm/test/Transforms/PhaseOrdering/AArch64/vscale.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -passes="default<O1>" -mattr=+sve -S -o - %s | FileCheck %s

target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
target triple = "aarch64"

define i64 @udiv() vscale_range(1, 16) {
; CHECK-LABEL: @udiv(
; CHECK-NEXT:    ret i64 4
;
  %a = call i64 @llvm.aarch64.sve.cntb(i32 31)
  %b = call i64 @llvm.aarch64.sve.cntw(i32 31)
  %c = udiv i64 %a, %b
  ret i64 %c
}