| ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 |
| ; RUN: opt -p loop-vectorize -mtriple=arm64-apple-macosx -S %s | FileCheck %s |
| |
| target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" |
| |
| define i32 @multi_exit_iv_uniform(i32 %a, i64 %N, ptr %dst) { |
| ; CHECK-LABEL: define i32 @multi_exit_iv_uniform( |
| ; CHECK-SAME: i32 [[A:%.*]], i64 [[N:%.*]], ptr [[DST:%.*]]) { |
| ; CHECK-NEXT: entry: |
| ; CHECK-NEXT: [[UMIN:%.*]] = call i64 @llvm.umin.i64(i64 [[N]], i64 2147483648) |
| ; CHECK-NEXT: [[TMP0:%.*]] = add nuw nsw i64 [[UMIN]], 1 |
| ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ule i64 [[TMP0]], 8 |
| ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] |
| ; CHECK: vector.ph: |
| ; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP0]], 8 |
| ; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 [[N_MOD_VF]], 0 |
| ; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i64 8, i64 [[N_MOD_VF]] |
| ; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[TMP2]] |
| ; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[A]], i64 0 |
| ; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer |
| ; CHECK-NEXT: [[TMP7:%.*]] = zext <4 x i32> [[BROADCAST_SPLAT]] to <4 x i64> |
| ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] |
| ; CHECK: vector.body: |
| ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP10:%.*]], [[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP11:%.*]], [[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i64, ptr [[DST]], i64 [[INDEX]] |
| ; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i64, ptr [[TMP5]], i64 4 |
| ; CHECK-NEXT: store <4 x i64> [[TMP7]], ptr [[TMP5]], align 8 |
| ; CHECK-NEXT: store <4 x i64> [[TMP7]], ptr [[TMP9]], align 8 |
| ; CHECK-NEXT: [[TMP10]] = add <4 x i32> [[VEC_PHI]], splat (i32 -1) |
| ; CHECK-NEXT: [[TMP11]] = add <4 x i32> [[VEC_PHI1]], splat (i32 -1) |
| ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8 |
| ; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] |
| ; CHECK-NEXT: br i1 [[TMP12]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] |
| ; CHECK: middle.block: |
| ; CHECK-NEXT: [[BIN_RDX:%.*]] = add <4 x i32> [[TMP11]], [[TMP10]] |
| ; CHECK-NEXT: [[TMP13:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[BIN_RDX]]) |
| ; CHECK-NEXT: br label [[SCALAR_PH]] |
| ; CHECK: scalar.ph: |
| ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] |
| ; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP13]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ] |
| ; CHECK-NEXT: br label [[LOOP_HEADER:%.*]] |
| ; CHECK: loop.header: |
| ; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP_LATCH:%.*]] ] |
| ; CHECK-NEXT: [[IV_2:%.*]] = phi i32 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[IV_2_NEXT:%.*]], [[LOOP_LATCH]] ] |
| ; CHECK-NEXT: [[C_1:%.*]] = icmp eq i64 [[IV]], [[N]] |
| ; CHECK-NEXT: br i1 [[C_1]], label [[EXIT_1:%.*]], label [[LOOP_LATCH]] |
| ; CHECK: loop.latch: |
| ; CHECK-NEXT: [[ARRAYIDX_I:%.*]] = getelementptr i64, ptr [[DST]], i64 [[IV]] |
| ; CHECK-NEXT: [[CONV7:%.*]] = zext i32 [[A]] to i64 |
| ; CHECK-NEXT: store i64 [[CONV7]], ptr [[ARRAYIDX_I]], align 8 |
| ; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 |
| ; CHECK-NEXT: [[IV_2_NEXT]] = add i32 [[IV_2]], -1 |
| ; CHECK-NEXT: [[C_2:%.*]] = icmp eq i64 [[IV]], 2147483648 |
| ; CHECK-NEXT: br i1 [[C_2]], label [[EXIT_2:%.*]], label [[LOOP_HEADER]], !llvm.loop [[LOOP3:![0-9]+]] |
| ; CHECK: exit.1: |
| ; CHECK-NEXT: ret i32 10 |
| ; CHECK: exit.2: |
| ; CHECK-NEXT: [[IV_2_NEXT_LCSSA:%.*]] = phi i32 [ [[IV_2_NEXT]], [[LOOP_LATCH]] ] |
| ; CHECK-NEXT: ret i32 [[IV_2_NEXT_LCSSA]] |
| ; |
| entry: |
| br label %loop.header |
| |
| loop.header: |
| %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ] |
| %iv.2 = phi i32 [ 0, %entry ], [ %iv.2.next, %loop.latch ] |
| %c.1 = icmp eq i64 %iv, %N |
| br i1 %c.1, label %exit.1, label %loop.latch |
| |
| loop.latch: |
| %arrayidx.i = getelementptr i64, ptr %dst, i64 %iv |
| %conv7 = zext i32 %a to i64 |
| store i64 %conv7, ptr %arrayidx.i, align 8 |
| %iv.next = add i64 %iv, 1 |
| %iv.2.next = add i32 %iv.2, -1 |
| %c.2 = icmp eq i64 %iv, 2147483648 |
| br i1 %c.2, label %exit.2, label %loop.header |
| |
| exit.1: |
| ret i32 10 |
| |
| exit.2: |
| ret i32 %iv.2.next |
| } |
| |
| define i64 @pointer_induction_only(ptr %start, ptr %end) { |
| ; CHECK-LABEL: define i64 @pointer_induction_only( |
| ; CHECK-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) { |
| ; CHECK-NEXT: entry: |
| ; CHECK-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64 |
| ; CHECK-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64 |
| ; CHECK-NEXT: [[TMP0:%.*]] = sub i64 [[END1]], [[START2]] |
| ; CHECK-NEXT: [[TMP1:%.*]] = lshr i64 [[TMP0]], 2 |
| ; CHECK-NEXT: [[TMP2:%.*]] = add nuw nsw i64 [[TMP1]], 1 |
| ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP2]], 8 |
| ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] |
| ; CHECK: vector.ph: |
| ; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP2]], 4 |
| ; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP2]], [[N_MOD_VF]] |
| ; CHECK-NEXT: [[TMP3:%.*]] = mul i64 [[N_VEC]], 4 |
| ; CHECK-NEXT: [[IND_END:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP3]] |
| ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] |
| ; CHECK: vector.body: |
| ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 4 |
| ; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[START]], i64 [[OFFSET_IDX]] |
| ; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i32, ptr [[NEXT_GEP]], i64 2 |
| ; CHECK-NEXT: [[WIDE_LOAD4:%.*]] = load <2 x i32>, ptr [[TMP7]], align 1 |
| ; CHECK-NEXT: [[TMP9:%.*]] = zext <2 x i32> [[WIDE_LOAD4]] to <2 x i64> |
| ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 |
| ; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] |
| ; CHECK-NEXT: br i1 [[TMP12]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] |
| ; CHECK: middle.block: |
| ; CHECK-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement <2 x i64> [[TMP9]], i32 1 |
| ; CHECK-NEXT: [[VECTOR_RECUR_EXTRACT_FOR_PHI:%.*]] = extractelement <2 x i64> [[TMP9]], i32 0 |
| ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP2]], [[N_VEC]] |
| ; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]] |
| ; CHECK: scalar.ph: |
| ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi ptr [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ [[START]], [[ENTRY:%.*]] ] |
| ; CHECK-NEXT: [[SCALAR_RECUR_INIT:%.*]] = phi i64 [ [[VECTOR_RECUR_EXTRACT]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ] |
| ; CHECK-NEXT: br label [[LOOP:%.*]] |
| ; CHECK: loop: |
| ; CHECK-NEXT: [[IV:%.*]] = phi ptr [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ] |
| ; CHECK-NEXT: [[SCALAR_RECUR:%.*]] = phi i64 [ [[SCALAR_RECUR_INIT]], [[SCALAR_PH]] ], [ [[RECUR_NEXT:%.*]], [[LOOP]] ] |
| ; CHECK-NEXT: [[L:%.*]] = load i32, ptr [[IV]], align 1 |
| ; CHECK-NEXT: [[RECUR_NEXT]] = zext i32 [[L]] to i64 |
| ; CHECK-NEXT: [[IV_NEXT]] = getelementptr inbounds i8, ptr [[IV]], i64 4 |
| ; CHECK-NEXT: [[C:%.*]] = icmp eq ptr [[IV]], [[END]] |
| ; CHECK-NEXT: br i1 [[C]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP5:![0-9]+]] |
| ; CHECK: exit: |
| ; CHECK-NEXT: [[RECUR_LCSSA:%.*]] = phi i64 [ [[SCALAR_RECUR]], [[LOOP]] ], [ [[VECTOR_RECUR_EXTRACT_FOR_PHI]], [[MIDDLE_BLOCK]] ] |
| ; CHECK-NEXT: ret i64 [[RECUR_LCSSA]] |
| ; |
| entry: |
| br label %loop |
| |
| loop: |
| %iv = phi ptr [ %start, %entry ], [ %iv.next, %loop ] |
| %recur = phi i64 [ 0, %entry ], [ %recur.next, %loop ] |
| %l = load i32, ptr %iv, align 1 |
| %recur.next = zext i32 %l to i64 |
| %iv.next = getelementptr inbounds i8, ptr %iv, i64 4 |
| %c = icmp eq ptr %iv, %end |
| br i1 %c, label %exit, label %loop |
| |
| exit: |
| ret i64 %recur |
| } |
| |
| |
| define i64 @int_and_pointer_iv(ptr %start, i32 %N) { |
| ; CHECK-LABEL: define i64 @int_and_pointer_iv( |
| ; CHECK-SAME: ptr [[START:%.*]], i32 [[N:%.*]]) { |
| ; CHECK-NEXT: entry: |
| ; CHECK-NEXT: br label [[VECTOR_PH:%.*]] |
| ; CHECK: vector.ph: |
| ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] |
| ; CHECK: vector.body: |
| ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 4 |
| ; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[START]], i64 [[OFFSET_IDX]] |
| ; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i32, ptr [[NEXT_GEP]], i64 4 |
| ; CHECK-NEXT: [[WIDE_LOAD3:%.*]] = load <4 x i32>, ptr [[TMP3]], align 4 |
| ; CHECK-NEXT: [[TMP5:%.*]] = zext <4 x i32> [[WIDE_LOAD3]] to <4 x i64> |
| ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8 |
| ; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], 1000 |
| ; CHECK-NEXT: br i1 [[TMP8]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]] |
| ; CHECK: middle.block: |
| ; CHECK-NEXT: [[VECTOR_RECUR_EXTRACT_FOR_PHI:%.*]] = extractelement <4 x i64> [[TMP5]], i32 2 |
| ; CHECK-NEXT: br label [[LOOP:%.*]] |
| ; CHECK: exit: |
| ; CHECK-NEXT: ret i64 [[VECTOR_RECUR_EXTRACT_FOR_PHI]] |
| ; |
| entry: |
| br label %loop |
| |
| loop: |
| %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ] |
| %ptr.iv = phi ptr [ %start, %entry ], [ %ptr.iv.next, %loop ] |
| %recur = phi i64 [ 0, %entry ], [ %recur.next, %loop ] |
| %l = load i32, ptr %ptr.iv, align 4 |
| %recur.next = zext i32 %l to i64 |
| %ptr.iv.next = getelementptr i8, ptr %ptr.iv, i64 4 |
| %iv.next = add i32 %iv, 1 |
| %tobool.not = icmp eq i32 %iv.next, 1000 |
| br i1 %tobool.not, label %exit, label %loop |
| |
| exit: |
| ret i64 %recur |
| } |
| |
| define void @wide_truncated_iv(ptr %dst) { |
| ; CHECK-LABEL: define void @wide_truncated_iv( |
| ; CHECK-SAME: ptr [[DST:%.*]]) { |
| ; CHECK-NEXT: iter.check: |
| ; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] |
| ; CHECK: vector.main.loop.iter.check: |
| ; CHECK-NEXT: br i1 false, label [[VEC_EPILOG_PH:%.*]], label [[VECTOR_PH1:%.*]] |
| ; CHECK: vector.ph: |
| ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] |
| ; CHECK: vector.body: |
| ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH1]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[VEC_IND:%.*]] = phi <8 x i8> [ <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7>, [[VECTOR_PH1]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[STEP_ADD:%.*]] = add <8 x i8> [[VEC_IND]], splat (i8 8) |
| ; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[DST]], i64 [[INDEX]] |
| ; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[TMP2]], i64 8 |
| ; CHECK-NEXT: store <8 x i8> [[VEC_IND]], ptr [[TMP2]], align 1 |
| ; CHECK-NEXT: store <8 x i8> [[STEP_ADD]], ptr [[TMP5]], align 1 |
| ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 |
| ; CHECK-NEXT: [[VEC_IND_NEXT]] = add <8 x i8> [[STEP_ADD]], splat (i8 8) |
| ; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], 192 |
| ; CHECK-NEXT: br i1 [[TMP6]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]] |
| ; CHECK: middle.block: |
| ; CHECK-NEXT: br i1 false, label [[EXIT:%.*]], label [[VEC_EPILOG_ITER_CHECK:%.*]] |
| ; CHECK: vec.epilog.iter.check: |
| ; CHECK-NEXT: br i1 false, label [[SCALAR_PH]], label [[VEC_EPILOG_PH]], !prof [[PROF8:![0-9]+]] |
| ; CHECK: vec.epilog.ph: |
| ; CHECK-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i64 [ 192, [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[VECTOR_PH]] ] |
| ; CHECK-NEXT: [[TMP7:%.*]] = trunc i64 [[VEC_EPILOG_RESUME_VAL]] to i8 |
| ; CHECK-NEXT: [[DOTSPLATINSERT:%.*]] = insertelement <8 x i8> poison, i8 [[TMP7]], i64 0 |
| ; CHECK-NEXT: [[DOTSPLAT:%.*]] = shufflevector <8 x i8> [[DOTSPLATINSERT]], <8 x i8> poison, <8 x i32> zeroinitializer |
| ; CHECK-NEXT: [[INDUCTION:%.*]] = add <8 x i8> [[DOTSPLAT]], <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7> |
| ; CHECK-NEXT: br label [[LOOP:%.*]] |
| ; CHECK: vec.epilog.vector.body: |
| ; CHECK-NEXT: [[INDEX3:%.*]] = phi i64 [ [[VEC_EPILOG_RESUME_VAL]], [[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT7:%.*]], [[LOOP]] ] |
| ; CHECK-NEXT: [[VEC_IND4:%.*]] = phi <8 x i8> [ [[INDUCTION]], [[VEC_EPILOG_PH]] ], [ [[VEC_IND_NEXT6:%.*]], [[LOOP]] ] |
| ; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i8, ptr [[DST]], i64 [[INDEX3]] |
| ; CHECK-NEXT: store <8 x i8> [[VEC_IND4]], ptr [[TMP9]], align 1 |
| ; CHECK-NEXT: [[INDEX_NEXT7]] = add nuw i64 [[INDEX3]], 8 |
| ; CHECK-NEXT: [[VEC_IND_NEXT6]] = add <8 x i8> [[VEC_IND4]], splat (i8 8) |
| ; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i64 [[INDEX_NEXT7]], 200 |
| ; CHECK-NEXT: br i1 [[TMP11]], label [[VEC_EPILOG_MIDDLE_BLOCK:%.*]], label [[LOOP]], !llvm.loop [[LOOP9:![0-9]+]] |
| ; CHECK: vec.epilog.middle.block: |
| ; CHECK-NEXT: br i1 false, label [[EXIT]], label [[SCALAR_PH]] |
| ; CHECK: vec.epilog.scalar.ph: |
| ; CHECK-NEXT: [[BC_RESUME_VAL2:%.*]] = phi i64 [ 200, [[VEC_EPILOG_MIDDLE_BLOCK]] ], [ 192, [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[ITER_CHECK:%.*]] ] |
| ; CHECK-NEXT: br label [[LOOP1:%.*]] |
| ; CHECK: loop: |
| ; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL2]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP1]] ] |
| ; CHECK-NEXT: [[TRUNC_IV:%.*]] = trunc i64 [[IV]] to i8 |
| ; CHECK-NEXT: [[GEP:%.*]] = getelementptr i8, ptr [[DST]], i64 [[IV]] |
| ; CHECK-NEXT: store i8 [[TRUNC_IV]], ptr [[GEP]], align 1 |
| ; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 |
| ; CHECK-NEXT: [[C:%.*]] = icmp eq i64 [[IV]], 200 |
| ; CHECK-NEXT: br i1 [[C]], label [[EXIT]], label [[LOOP1]], !llvm.loop [[LOOP10:![0-9]+]] |
| ; CHECK: exit: |
| ; CHECK-NEXT: ret void |
| ; |
| entry: |
| br label %loop |
| |
| loop: |
| %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] |
| %trunc.iv = trunc i64 %iv to i8 |
| %gep = getelementptr i8, ptr %dst, i64 %iv |
| store i8 %trunc.iv, ptr %gep, align 1 |
| %iv.next = add i64 %iv, 1 |
| %c = icmp eq i64 %iv, 200 |
| br i1 %c, label %exit, label %loop |
| |
| exit: |
| ret void |
| } |
| |
| define i64 @test_ptr_ivs_and_widened_ivs(ptr %src, i32 %N) { |
| ; CHECK-LABEL: define i64 @test_ptr_ivs_and_widened_ivs( |
| ; CHECK-SAME: ptr [[SRC:%.*]], i32 [[N:%.*]]) { |
| ; CHECK-NEXT: entry: |
| ; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N]], -1 |
| ; CHECK-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 |
| ; CHECK-NEXT: [[TMP2:%.*]] = add nuw nsw i64 [[TMP1]], 1 |
| ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP2]], 8 |
| ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] |
| ; CHECK: vector.ph: |
| ; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP2]], 8 |
| ; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP2]], [[N_MOD_VF]] |
| ; CHECK-NEXT: [[TMP3:%.*]] = mul i64 [[N_VEC]], 4 |
| ; CHECK-NEXT: [[IND_END:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[TMP3]] |
| ; CHECK-NEXT: [[IND_END1:%.*]] = trunc i64 [[N_VEC]] to i32 |
| ; CHECK-NEXT: [[IND_END3:%.*]] = trunc i64 [[N_VEC]] to i32 |
| ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] |
| ; CHECK: vector.body: |
| ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[STEP_ADD:%.*]] = add <4 x i32> [[VEC_IND]], splat (i32 4) |
| ; CHECK-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 4 |
| ; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[OFFSET_IDX]] |
| ; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i32, ptr [[NEXT_GEP]], i64 4 |
| ; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP6]], align 4 |
| ; CHECK-NEXT: [[TMP7:%.*]] = xor <4 x i32> [[WIDE_LOAD]], splat (i32 1) |
| ; CHECK-NEXT: [[TMP8:%.*]] = zext <4 x i32> [[TMP7]] to <4 x i64> |
| ; CHECK-NEXT: [[TMP9:%.*]] = zext <4 x i32> [[STEP_ADD]] to <4 x i64> |
| ; CHECK-NEXT: [[TMP10:%.*]] = shl <4 x i64> [[TMP8]], [[TMP9]] |
| ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8 |
| ; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[STEP_ADD]], splat (i32 4) |
| ; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] |
| ; CHECK-NEXT: br i1 [[TMP11]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]] |
| ; CHECK: middle.block: |
| ; CHECK-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement <4 x i64> [[TMP10]], i32 3 |
| ; CHECK-NEXT: [[VECTOR_RECUR_EXTRACT_FOR_PHI:%.*]] = extractelement <4 x i64> [[TMP10]], i32 2 |
| ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP2]], [[N_VEC]] |
| ; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]] |
| ; CHECK: scalar.ph: |
| ; CHECK-NEXT: [[SCALAR_RECUR_INIT:%.*]] = phi i64 [ [[VECTOR_RECUR_EXTRACT]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] |
| ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi ptr [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ [[SRC]], [[ENTRY]] ] |
| ; CHECK-NEXT: [[BC_RESUME_VAL2:%.*]] = phi i32 [ [[IND_END1]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ] |
| ; CHECK-NEXT: [[BC_RESUME_VAL4:%.*]] = phi i32 [ [[IND_END3]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ] |
| ; CHECK-NEXT: br label [[LOOP:%.*]] |
| ; CHECK: loop: |
| ; CHECK-NEXT: [[P:%.*]] = phi i64 [ [[SCALAR_RECUR_INIT]], [[SCALAR_PH]] ], [ [[SHL:%.*]], [[LOOP]] ] |
| ; CHECK-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[PTR_IV_NEXT:%.*]], [[LOOP]] ] |
| ; CHECK-NEXT: [[IV_1:%.*]] = phi i32 [ [[BC_RESUME_VAL2]], [[SCALAR_PH]] ], [ [[IV_1_NEXT:%.*]], [[LOOP]] ] |
| ; CHECK-NEXT: [[IV_2:%.*]] = phi i32 [ [[BC_RESUME_VAL4]], [[SCALAR_PH]] ], [ [[IV_2_NEXT:%.*]], [[LOOP]] ] |
| ; CHECK-NEXT: [[L:%.*]] = load i32, ptr [[PTR_IV]], align 4 |
| ; CHECK-NEXT: [[NOT:%.*]] = xor i32 [[L]], 1 |
| ; CHECK-NEXT: [[NOT_EXT:%.*]] = zext i32 [[NOT]] to i64 |
| ; CHECK-NEXT: [[IV_EXT:%.*]] = zext i32 [[IV_1]] to i64 |
| ; CHECK-NEXT: [[SHL]] = shl i64 [[NOT_EXT]], [[IV_EXT]] |
| ; CHECK-NEXT: [[PTR_IV_NEXT]] = getelementptr i8, ptr [[PTR_IV]], i64 4 |
| ; CHECK-NEXT: [[IV_1_NEXT]] = add i32 [[IV_1]], 1 |
| ; CHECK-NEXT: [[IV_2_NEXT]] = add i32 [[IV_2]], 1 |
| ; CHECK-NEXT: [[EC:%.*]] = icmp eq i32 [[IV_2_NEXT]], [[N]] |
| ; CHECK-NEXT: br i1 [[EC]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP12:![0-9]+]] |
| ; CHECK: exit: |
| ; CHECK-NEXT: [[P_LCSSA:%.*]] = phi i64 [ [[P]], [[LOOP]] ], [ [[VECTOR_RECUR_EXTRACT_FOR_PHI]], [[MIDDLE_BLOCK]] ] |
| ; CHECK-NEXT: ret i64 [[P_LCSSA]] |
| ; |
| entry: |
| br label %loop |
| |
| loop: |
| %p = phi i64 [ 0, %entry ], [ %shl, %loop ] |
| %ptr.iv = phi ptr [ %src, %entry ], [ %ptr.iv.next, %loop ] |
| %iv.1 = phi i32 [ 0, %entry ], [ %iv.1.next, %loop ] |
| %iv.2 = phi i32 [ 0, %entry ], [ %iv.2.next, %loop ] |
| %l = load i32, ptr %ptr.iv, align 4 |
| %not = xor i32 %l, 1 |
| %not.ext = zext i32 %not to i64 |
| %iv.ext = zext i32 %iv.1 to i64 |
| %shl = shl i64 %not.ext , %iv.ext |
| %ptr.iv.next = getelementptr i8, ptr %ptr.iv, i64 4 |
| %iv.1.next = add i32 %iv.1, 1 |
| %iv.2.next = add i32 %iv.2, 1 |
| %ec = icmp eq i32 %iv.2.next, %N |
| br i1 %ec, label %exit, label %loop |
| |
| exit: |
| ret i64 %p |
| } |
| |
| define void @zext_iv_increment(ptr %dst, i64 %N) { |
| ; CHECK-LABEL: define void @zext_iv_increment( |
| ; CHECK-SAME: ptr [[DST:%.*]], i64 [[N:%.*]]) { |
| ; CHECK-NEXT: entry: |
| ; CHECK-NEXT: [[UMAX1:%.*]] = call i64 @llvm.umax.i64(i64 [[N]], i64 1) |
| ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[UMAX1]], 2 |
| ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]] |
| ; CHECK: vector.scevcheck: |
| ; CHECK-NEXT: [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[N]], i64 1) |
| ; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[UMAX]], -1 |
| ; CHECK-NEXT: [[TMP2:%.*]] = trunc i64 [[TMP0]] to i32 |
| ; CHECK-NEXT: [[TMP3:%.*]] = add i32 1, [[TMP2]] |
| ; CHECK-NEXT: [[TMP4:%.*]] = icmp ult i32 [[TMP3]], 1 |
| ; CHECK-NEXT: [[TMP5:%.*]] = icmp ugt i64 [[TMP0]], 4294967295 |
| ; CHECK-NEXT: [[TMP6:%.*]] = or i1 [[TMP4]], [[TMP5]] |
| ; CHECK-NEXT: br i1 [[TMP6]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] |
| ; CHECK: vector.ph: |
| ; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[UMAX1]], 2 |
| ; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[UMAX1]], [[N_MOD_VF]] |
| ; CHECK-NEXT: [[IND_END:%.*]] = trunc i64 [[N_VEC]] to i32 |
| ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] |
| ; CHECK: vector.body: |
| ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[INDEX]], 1 |
| ; CHECK-NEXT: [[TMP9:%.*]] = getelementptr { i32, i32, i32 }, ptr [[DST]], i64 [[INDEX]], i32 2 |
| ; CHECK-NEXT: [[TMP10:%.*]] = getelementptr { i32, i32, i32 }, ptr [[DST]], i64 [[TMP8]], i32 2 |
| ; CHECK-NEXT: store i32 0, ptr [[TMP9]], align 8 |
| ; CHECK-NEXT: store i32 0, ptr [[TMP10]], align 8 |
| ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 |
| ; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] |
| ; CHECK-NEXT: br i1 [[TMP11]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP13:![0-9]+]] |
| ; CHECK: middle.block: |
| ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[UMAX1]], [[N_VEC]] |
| ; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]] |
| ; CHECK: scalar.ph: |
| ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ], [ 0, [[VECTOR_SCEVCHECK]] ] |
| ; CHECK-NEXT: [[BC_RESUME_VAL2:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ], [ 0, [[VECTOR_SCEVCHECK]] ] |
| ; CHECK-NEXT: br label [[LOOP:%.*]] |
| ; CHECK: loop: |
| ; CHECK-NEXT: [[IV:%.*]] = phi i32 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ] |
| ; CHECK-NEXT: [[IV_WIDE:%.*]] = phi i64 [ [[BC_RESUME_VAL2]], [[SCALAR_PH]] ], [ [[IV_NEXT_EXT:%.*]], [[LOOP]] ] |
| ; CHECK-NEXT: [[PATCH_INDEX:%.*]] = getelementptr { i32, i32, i32 }, ptr [[DST]], i64 [[IV_WIDE]], i32 2 |
| ; CHECK-NEXT: store i32 0, ptr [[PATCH_INDEX]], align 8 |
| ; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1 |
| ; CHECK-NEXT: [[IV_NEXT_EXT]] = zext i32 [[IV_NEXT]] to i64 |
| ; CHECK-NEXT: [[EC:%.*]] = icmp ult i64 [[IV_NEXT_EXT]], [[N]] |
| ; CHECK-NEXT: br i1 [[EC]], label [[LOOP]], label [[EXIT]], !llvm.loop [[LOOP14:![0-9]+]] |
| ; CHECK: exit: |
| ; CHECK-NEXT: ret void |
| ; |
| entry: |
| br label %loop |
| |
| loop: |
| %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ] |
| %iv.wide = phi i64 [ 0, %entry ], [ %iv.next.ext, %loop ] |
| %patch_index = getelementptr { i32, i32, i32 }, ptr %dst, i64 %iv.wide, i32 2 |
| store i32 0, ptr %patch_index, align 8 |
| %iv.next = add i32 %iv, 1 |
| %iv.next.ext = zext i32 %iv.next to i64 |
| %ec = icmp ult i64 %iv.next.ext, %N |
| br i1 %ec, label %loop, label %exit |
| |
| exit: |
| ret void |
| } |
| |
| define i32 @load_from_pointer_induction(ptr %start, ptr %end) { |
| ; CHECK-LABEL: define i32 @load_from_pointer_induction( |
| ; CHECK-SAME: ptr [[START:%.*]], ptr [[END:%.*]]) { |
| ; CHECK-NEXT: entry: |
| ; CHECK-NEXT: [[START2:%.*]] = ptrtoint ptr [[START]] to i64 |
| ; CHECK-NEXT: [[END1:%.*]] = ptrtoint ptr [[END]] to i64 |
| ; CHECK-NEXT: [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[END1]], i64 [[START2]]) |
| ; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[UMAX]], 1 |
| ; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[START2]] |
| ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP1]], 2 |
| ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] |
| ; CHECK: vector.ph: |
| ; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP1]], 2 |
| ; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP1]], [[N_MOD_VF]] |
| ; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[START]], i64 [[N_VEC]] |
| ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] |
| ; CHECK: vector.body: |
| ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[VEC_PHI:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[TMP8:%.*]], [[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[VEC_PHI3:%.*]] = phi i32 [ 0, [[VECTOR_PH]] ], [ [[TMP9:%.*]], [[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 1 |
| ; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[START]], i64 [[INDEX]] |
| ; CHECK-NEXT: [[NEXT_GEP4:%.*]] = getelementptr i8, ptr [[START]], i64 [[TMP3]] |
| ; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[NEXT_GEP]], align 1 |
| ; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[NEXT_GEP4]], align 1 |
| ; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[TMP4]], 1 |
| ; CHECK-NEXT: [[TMP7:%.*]] = and i32 [[TMP5]], 1 |
| ; CHECK-NEXT: [[TMP8]] = or i32 [[VEC_PHI]], [[TMP6]] |
| ; CHECK-NEXT: [[TMP9]] = or i32 [[VEC_PHI3]], [[TMP7]] |
| ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 |
| ; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] |
| ; CHECK-NEXT: br i1 [[TMP10]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP15:![0-9]+]] |
| ; CHECK: middle.block: |
| ; CHECK-NEXT: [[BIN_RDX:%.*]] = or i32 [[TMP9]], [[TMP8]] |
| ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP1]], [[N_VEC]] |
| ; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]] |
| ; CHECK: scalar.ph: |
| ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi ptr [ [[TMP2]], [[MIDDLE_BLOCK]] ], [ [[START]], [[ENTRY:%.*]] ] |
| ; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[BIN_RDX]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ] |
| ; CHECK-NEXT: br label [[LOOP:%.*]] |
| ; CHECK: loop: |
| ; CHECK-NEXT: [[IV:%.*]] = phi ptr [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ] |
| ; CHECK-NEXT: [[RDX:%.*]] = phi i32 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[RDX_NEXT:%.*]], [[LOOP]] ] |
| ; CHECK-NEXT: [[L:%.*]] = load i32, ptr [[IV]], align 1 |
| ; CHECK-NEXT: [[TMP11:%.*]] = and i32 [[L]], 1 |
| ; CHECK-NEXT: [[RDX_NEXT]] = or i32 [[RDX]], [[TMP11]] |
| ; CHECK-NEXT: [[IV_NEXT]] = getelementptr i8, ptr [[IV]], i64 1 |
| ; CHECK-NEXT: [[EC:%.*]] = icmp ult ptr [[IV]], [[END]] |
| ; CHECK-NEXT: br i1 [[EC]], label [[LOOP]], label [[EXIT]], !llvm.loop [[LOOP16:![0-9]+]] |
| ; CHECK: exit: |
| ; CHECK-NEXT: [[RDX_NEXT_LCSSA:%.*]] = phi i32 [ [[RDX_NEXT]], [[LOOP]] ], [ [[BIN_RDX]], [[MIDDLE_BLOCK]] ] |
| ; CHECK-NEXT: ret i32 [[RDX_NEXT_LCSSA]] |
| ; |
| entry: |
| br label %loop |
| |
| loop: |
| %iv = phi ptr [ %start, %entry ], [ %iv.next, %loop ] |
| %rdx = phi i32 [ 0, %entry ], [ %rdx.next, %loop ] |
| %l = load i32, ptr %iv, align 1 |
| %1 = and i32 %l, 1 |
| %rdx.next = or i32 %rdx, %1 |
| %iv.next = getelementptr i8, ptr %iv, i64 1 |
| %ec = icmp ult ptr %iv, %end |
| br i1 %ec, label %loop, label %exit |
| |
| exit: |
| ret i32 %rdx.next |
| } |
| |
| ; Test that sext(sub nsw) used in address computation is handled correctly |
| ; in VPlan cost model (must match SCEV's handling). |
| define void@sext_sub_nsw_for_address(ptr %base, i64 %n, ptr %src) #0 { |
| ; |
| ; CHECK-LABEL: define void @sext_sub_nsw_for_address( |
| ; CHECK-SAME: ptr [[BASE:%.*]], i64 [[N:%.*]], ptr [[SRC:%.*]]) #[[ATTR0:[0-9]+]] { |
| ; CHECK-NEXT: iter.check: |
| ; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[N]], 1 |
| ; CHECK-NEXT: [[SMIN15:%.*]] = call i64 @llvm.smin.i64(i64 [[N]], i64 0) |
| ; CHECK-NEXT: [[TMP1:%.*]] = sub i64 [[TMP0]], [[SMIN15]] |
| ; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP1]], 2 |
| ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[VEC_EPILOG_SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]] |
| ; CHECK: vector.scevcheck: |
| ; CHECK-NEXT: [[SMIN:%.*]] = call i64 @llvm.smin.i64(i64 [[N]], i64 0) |
| ; CHECK-NEXT: [[TMP2:%.*]] = sub i64 [[N]], [[SMIN]] |
| ; CHECK-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[SRC]], i64 -8 |
| ; CHECK-NEXT: [[MUL:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 16, i64 [[TMP2]]) |
| ; CHECK-NEXT: [[MUL_RESULT:%.*]] = extractvalue { i64, i1 } [[MUL]], 0 |
| ; CHECK-NEXT: [[MUL_OVERFLOW:%.*]] = extractvalue { i64, i1 } [[MUL]], 1 |
| ; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[SCEVGEP]], i64 [[MUL_RESULT]] |
| ; CHECK-NEXT: [[TMP4:%.*]] = icmp ult ptr [[TMP3]], [[SCEVGEP]] |
| ; CHECK-NEXT: [[TMP5:%.*]] = or i1 [[TMP4]], [[MUL_OVERFLOW]] |
| ; CHECK-NEXT: [[MUL1:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 16, i64 [[TMP2]]) |
| ; CHECK-NEXT: [[MUL_RESULT2:%.*]] = extractvalue { i64, i1 } [[MUL1]], 0 |
| ; CHECK-NEXT: [[MUL_OVERFLOW3:%.*]] = extractvalue { i64, i1 } [[MUL1]], 1 |
| ; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[MUL_RESULT2]] |
| ; CHECK-NEXT: [[TMP7:%.*]] = icmp ult ptr [[TMP6]], [[SRC]] |
| ; CHECK-NEXT: [[TMP8:%.*]] = or i1 [[TMP7]], [[MUL_OVERFLOW3]] |
| ; CHECK-NEXT: [[TMP9:%.*]] = trunc i64 [[TMP2]] to i32 |
| ; CHECK-NEXT: [[MUL4:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 2, i32 [[TMP9]]) |
| ; CHECK-NEXT: [[MUL_RESULT5:%.*]] = extractvalue { i32, i1 } [[MUL4]], 0 |
| ; CHECK-NEXT: [[MUL_OVERFLOW6:%.*]] = extractvalue { i32, i1 } [[MUL4]], 1 |
| ; CHECK-NEXT: [[TMP10:%.*]] = icmp slt i32 [[MUL_RESULT5]], 0 |
| ; CHECK-NEXT: [[TMP11:%.*]] = or i1 [[TMP10]], [[MUL_OVERFLOW6]] |
| ; CHECK-NEXT: [[TMP12:%.*]] = icmp ugt i64 [[TMP2]], 4294967295 |
| ; CHECK-NEXT: [[TMP13:%.*]] = or i1 [[TMP11]], [[TMP12]] |
| ; CHECK-NEXT: [[MUL7:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 16, i64 [[TMP2]]) |
| ; CHECK-NEXT: [[MUL_RESULT8:%.*]] = extractvalue { i64, i1 } [[MUL7]], 0 |
| ; CHECK-NEXT: [[MUL_OVERFLOW9:%.*]] = extractvalue { i64, i1 } [[MUL7]], 1 |
| ; CHECK-NEXT: [[TMP14:%.*]] = sub i64 0, [[MUL_RESULT8]] |
| ; CHECK-NEXT: [[TMP15:%.*]] = getelementptr i8, ptr [[BASE]], i64 [[TMP14]] |
| ; CHECK-NEXT: [[TMP16:%.*]] = icmp ugt ptr [[TMP15]], [[BASE]] |
| ; CHECK-NEXT: [[TMP17:%.*]] = or i1 [[TMP16]], [[MUL_OVERFLOW9]] |
| ; CHECK-NEXT: [[TMP18:%.*]] = or i1 [[TMP5]], [[TMP8]] |
| ; CHECK-NEXT: [[TMP19:%.*]] = or i1 [[TMP18]], [[TMP13]] |
| ; CHECK-NEXT: [[TMP20:%.*]] = or i1 [[TMP19]], [[TMP17]] |
| ; CHECK-NEXT: br i1 [[TMP20]], label [[VEC_EPILOG_SCALAR_PH]], label [[VECTOR_MEMCHECK:%.*]] |
| ; CHECK: vector.memcheck: |
| ; CHECK-NEXT: [[SCEVGEP10:%.*]] = getelementptr i8, ptr [[SRC]], i64 -8 |
| ; CHECK-NEXT: [[TMP21:%.*]] = shl i64 [[N]], 4 |
| ; CHECK-NEXT: [[TMP22:%.*]] = add i64 [[TMP21]], 8 |
| ; CHECK-NEXT: [[SMIN11:%.*]] = call i64 @llvm.smin.i64(i64 [[N]], i64 0) |
| ; CHECK-NEXT: [[TMP23:%.*]] = shl i64 [[SMIN11]], 4 |
| ; CHECK-NEXT: [[TMP24:%.*]] = sub i64 [[TMP22]], [[TMP23]] |
| ; CHECK-NEXT: [[SCEVGEP12:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[TMP24]] |
| ; CHECK-NEXT: [[TMP25:%.*]] = sub i64 [[TMP23]], [[TMP21]] |
| ; CHECK-NEXT: [[SCEVGEP13:%.*]] = getelementptr i8, ptr [[BASE]], i64 [[TMP25]] |
| ; CHECK-NEXT: [[SCEVGEP14:%.*]] = getelementptr i8, ptr [[BASE]], i64 8 |
| ; CHECK-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[SCEVGEP10]], [[SCEVGEP14]] |
| ; CHECK-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[SCEVGEP13]], [[SCEVGEP12]] |
| ; CHECK-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]] |
| ; CHECK-NEXT: br i1 [[FOUND_CONFLICT]], label [[VEC_EPILOG_SCALAR_PH]], label [[VECTOR_MAIN_LOOP_ITER_CHECK:%.*]] |
| ; CHECK: vector.main.loop.iter.check: |
| ; CHECK-NEXT: [[MIN_ITERS_CHECK16:%.*]] = icmp ult i64 [[TMP1]], 8 |
| ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK16]], label [[VEC_EPILOG_PH:%.*]], label [[VECTOR_PH:%.*]] |
| ; CHECK: vector.ph: |
| ; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP1]], 8 |
| ; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP1]], [[N_MOD_VF]] |
| ; CHECK-NEXT: [[DOTCAST:%.*]] = trunc i64 [[N_VEC]] to i32 |
| ; CHECK-NEXT: [[TMP26:%.*]] = mul i32 [[DOTCAST]], 2 |
| ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] |
| ; CHECK: vector.body: |
| ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[VEC_IND:%.*]] = phi <2 x i32> [ <i32 0, i32 2>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[STEP_ADD:%.*]] = add <2 x i32> [[VEC_IND]], splat (i32 4) |
| ; CHECK-NEXT: [[STEP_ADD_2:%.*]] = add <2 x i32> [[STEP_ADD]], splat (i32 4) |
| ; CHECK-NEXT: [[STEP_ADD_3:%.*]] = add <2 x i32> [[STEP_ADD_2]], splat (i32 4) |
| ; CHECK-NEXT: [[TMP27:%.*]] = mul i64 [[INDEX]], 2 |
| ; CHECK-NEXT: [[TMP28:%.*]] = add i64 [[TMP27]], 4 |
| ; CHECK-NEXT: [[TMP29:%.*]] = add i64 [[TMP27]], 8 |
| ; CHECK-NEXT: [[TMP30:%.*]] = add i64 [[TMP27]], 12 |
| ; CHECK-NEXT: [[TMP31:%.*]] = getelementptr double, ptr [[SRC]], i64 [[TMP27]] |
| ; CHECK-NEXT: [[TMP32:%.*]] = getelementptr double, ptr [[SRC]], i64 [[TMP28]] |
| ; CHECK-NEXT: [[TMP33:%.*]] = getelementptr double, ptr [[SRC]], i64 [[TMP29]] |
| ; CHECK-NEXT: [[TMP34:%.*]] = getelementptr double, ptr [[SRC]], i64 [[TMP30]] |
| ; CHECK-NEXT: [[TMP35:%.*]] = getelementptr i8, ptr [[TMP31]], i64 -8 |
| ; CHECK-NEXT: [[TMP36:%.*]] = getelementptr i8, ptr [[TMP32]], i64 -8 |
| ; CHECK-NEXT: [[TMP37:%.*]] = getelementptr i8, ptr [[TMP33]], i64 -8 |
| ; CHECK-NEXT: [[TMP38:%.*]] = getelementptr i8, ptr [[TMP34]], i64 -8 |
| ; CHECK-NEXT: [[TMP39:%.*]] = sub nsw <2 x i32> zeroinitializer, [[VEC_IND]] |
| ; CHECK-NEXT: [[TMP40:%.*]] = sub nsw <2 x i32> zeroinitializer, [[STEP_ADD]] |
| ; CHECK-NEXT: [[TMP41:%.*]] = sub nsw <2 x i32> zeroinitializer, [[STEP_ADD_2]] |
| ; CHECK-NEXT: [[TMP42:%.*]] = sub nsw <2 x i32> zeroinitializer, [[STEP_ADD_3]] |
| ; CHECK-NEXT: [[TMP43:%.*]] = sext <2 x i32> [[TMP39]] to <2 x i64> |
| ; CHECK-NEXT: [[TMP44:%.*]] = extractelement <2 x i64> [[TMP43]], i32 0 |
| ; CHECK-NEXT: [[TMP45:%.*]] = extractelement <2 x i64> [[TMP43]], i32 1 |
| ; CHECK-NEXT: [[TMP46:%.*]] = sext <2 x i32> [[TMP40]] to <2 x i64> |
| ; CHECK-NEXT: [[TMP47:%.*]] = extractelement <2 x i64> [[TMP46]], i32 0 |
| ; CHECK-NEXT: [[TMP48:%.*]] = extractelement <2 x i64> [[TMP46]], i32 1 |
| ; CHECK-NEXT: [[TMP49:%.*]] = sext <2 x i32> [[TMP41]] to <2 x i64> |
| ; CHECK-NEXT: [[TMP50:%.*]] = extractelement <2 x i64> [[TMP49]], i32 0 |
| ; CHECK-NEXT: [[TMP51:%.*]] = extractelement <2 x i64> [[TMP49]], i32 1 |
| ; CHECK-NEXT: [[TMP52:%.*]] = sext <2 x i32> [[TMP42]] to <2 x i64> |
| ; CHECK-NEXT: [[TMP53:%.*]] = extractelement <2 x i64> [[TMP52]], i32 0 |
| ; CHECK-NEXT: [[TMP54:%.*]] = extractelement <2 x i64> [[TMP52]], i32 1 |
| ; CHECK-NEXT: [[TMP55:%.*]] = getelementptr double, ptr [[BASE]], i64 [[TMP44]] |
| ; CHECK-NEXT: [[TMP56:%.*]] = getelementptr double, ptr [[BASE]], i64 [[TMP45]] |
| ; CHECK-NEXT: [[TMP57:%.*]] = getelementptr double, ptr [[BASE]], i64 [[TMP47]] |
| ; CHECK-NEXT: [[TMP58:%.*]] = getelementptr double, ptr [[BASE]], i64 [[TMP48]] |
| ; CHECK-NEXT: [[TMP59:%.*]] = getelementptr double, ptr [[BASE]], i64 [[TMP50]] |
| ; CHECK-NEXT: [[TMP60:%.*]] = getelementptr double, ptr [[BASE]], i64 [[TMP51]] |
| ; CHECK-NEXT: [[TMP61:%.*]] = getelementptr double, ptr [[BASE]], i64 [[TMP53]] |
| ; CHECK-NEXT: [[TMP62:%.*]] = getelementptr double, ptr [[BASE]], i64 [[TMP54]] |
| ; CHECK-NEXT: [[TMP63:%.*]] = load double, ptr [[TMP55]], align 8, !alias.scope [[META17:![0-9]+]] |
| ; CHECK-NEXT: [[TMP64:%.*]] = load double, ptr [[TMP56]], align 8, !alias.scope [[META17]] |
| ; CHECK-NEXT: [[TMP65:%.*]] = insertelement <2 x double> poison, double [[TMP63]], i32 0 |
| ; CHECK-NEXT: [[TMP66:%.*]] = insertelement <2 x double> [[TMP65]], double [[TMP64]], i32 1 |
| ; CHECK-NEXT: [[TMP67:%.*]] = load double, ptr [[TMP57]], align 8, !alias.scope [[META17]] |
| ; CHECK-NEXT: [[TMP68:%.*]] = load double, ptr [[TMP58]], align 8, !alias.scope [[META17]] |
| ; CHECK-NEXT: [[TMP69:%.*]] = insertelement <2 x double> poison, double [[TMP67]], i32 0 |
| ; CHECK-NEXT: [[TMP70:%.*]] = insertelement <2 x double> [[TMP69]], double [[TMP68]], i32 1 |
| ; CHECK-NEXT: [[TMP71:%.*]] = load double, ptr [[TMP59]], align 8, !alias.scope [[META17]] |
| ; CHECK-NEXT: [[TMP72:%.*]] = load double, ptr [[TMP60]], align 8, !alias.scope [[META17]] |
| ; CHECK-NEXT: [[TMP73:%.*]] = insertelement <2 x double> poison, double [[TMP71]], i32 0 |
| ; CHECK-NEXT: [[TMP74:%.*]] = insertelement <2 x double> [[TMP73]], double [[TMP72]], i32 1 |
| ; CHECK-NEXT: [[TMP75:%.*]] = load double, ptr [[TMP61]], align 8, !alias.scope [[META17]] |
| ; CHECK-NEXT: [[TMP76:%.*]] = load double, ptr [[TMP62]], align 8, !alias.scope [[META17]] |
| ; CHECK-NEXT: [[TMP77:%.*]] = insertelement <2 x double> poison, double [[TMP75]], i32 0 |
| ; CHECK-NEXT: [[TMP78:%.*]] = insertelement <2 x double> [[TMP77]], double [[TMP76]], i32 1 |
| ; CHECK-NEXT: [[TMP79:%.*]] = shufflevector <2 x double> zeroinitializer, <2 x double> [[TMP66]], <4 x i32> <i32 0, i32 1, i32 2, i32 3> |
| ; CHECK-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <4 x double> [[TMP79]], <4 x double> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3> |
| ; CHECK-NEXT: store <4 x double> [[INTERLEAVED_VEC]], ptr [[TMP35]], align 8, !alias.scope [[META20:![0-9]+]], !noalias [[META17]] |
| ; CHECK-NEXT: [[TMP80:%.*]] = shufflevector <2 x double> zeroinitializer, <2 x double> [[TMP70]], <4 x i32> <i32 0, i32 1, i32 2, i32 3> |
| ; CHECK-NEXT: [[INTERLEAVED_VEC17:%.*]] = shufflevector <4 x double> [[TMP80]], <4 x double> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3> |
| ; CHECK-NEXT: store <4 x double> [[INTERLEAVED_VEC17]], ptr [[TMP36]], align 8, !alias.scope [[META20]], !noalias [[META17]] |
| ; CHECK-NEXT: [[TMP81:%.*]] = shufflevector <2 x double> zeroinitializer, <2 x double> [[TMP74]], <4 x i32> <i32 0, i32 1, i32 2, i32 3> |
| ; CHECK-NEXT: [[INTERLEAVED_VEC18:%.*]] = shufflevector <4 x double> [[TMP81]], <4 x double> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3> |
| ; CHECK-NEXT: store <4 x double> [[INTERLEAVED_VEC18]], ptr [[TMP37]], align 8, !alias.scope [[META20]], !noalias [[META17]] |
| ; CHECK-NEXT: [[TMP82:%.*]] = shufflevector <2 x double> zeroinitializer, <2 x double> [[TMP78]], <4 x i32> <i32 0, i32 1, i32 2, i32 3> |
| ; CHECK-NEXT: [[INTERLEAVED_VEC19:%.*]] = shufflevector <4 x double> [[TMP82]], <4 x double> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3> |
| ; CHECK-NEXT: store <4 x double> [[INTERLEAVED_VEC19]], ptr [[TMP38]], align 8, !alias.scope [[META20]], !noalias [[META17]] |
| ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8 |
| ; CHECK-NEXT: [[VEC_IND_NEXT]] = add <2 x i32> [[STEP_ADD_3]], splat (i32 4) |
| ; CHECK-NEXT: [[TMP83:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] |
| ; CHECK-NEXT: br i1 [[TMP83]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP22:![0-9]+]] |
| ; CHECK: middle.block: |
| ; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP1]], [[N_VEC]] |
| ; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[VEC_EPILOG_ITER_CHECK:%.*]] |
| ; CHECK: vec.epilog.iter.check: |
| ; CHECK-NEXT: [[IND_END:%.*]] = mul i64 [[N_VEC]], 2 |
| ; CHECK-NEXT: [[IND_END32:%.*]] = sub i64 [[N]], [[N_VEC]] |
| ; CHECK-NEXT: [[DOTCAST33:%.*]] = trunc i64 [[N_VEC]] to i32 |
| ; CHECK-NEXT: [[IND_END34:%.*]] = mul i32 [[DOTCAST33]], 2 |
| ; CHECK-NEXT: [[MIN_EPILOG_ITERS_CHECK:%.*]] = icmp ult i64 [[N_MOD_VF]], 2 |
| ; CHECK-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label [[VEC_EPILOG_SCALAR_PH]], label [[VEC_EPILOG_PH]], !prof [[PROF23:![0-9]+]] |
| ; CHECK: vec.epilog.ph: |
| ; CHECK-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[VECTOR_MAIN_LOOP_ITER_CHECK]] ] |
| ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[TMP26]], [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[VECTOR_MAIN_LOOP_ITER_CHECK]] ] |
| ; CHECK-NEXT: [[N_MOD_VF20:%.*]] = urem i64 [[TMP1]], 2 |
| ; CHECK-NEXT: [[N_VEC21:%.*]] = sub i64 [[TMP1]], [[N_MOD_VF20]] |
| ; CHECK-NEXT: [[TMP84:%.*]] = mul i64 [[N_VEC21]], 2 |
| ; CHECK-NEXT: [[TMP85:%.*]] = sub i64 [[N]], [[N_VEC21]] |
| ; CHECK-NEXT: [[DOTCAST22:%.*]] = trunc i64 [[N_VEC21]] to i32 |
| ; CHECK-NEXT: [[TMP86:%.*]] = mul i32 [[DOTCAST22]], 2 |
| ; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <2 x i32> poison, i32 [[BC_RESUME_VAL]], i64 0 |
| ; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <2 x i32> [[BROADCAST_SPLATINSERT]], <2 x i32> poison, <2 x i32> zeroinitializer |
| ; CHECK-NEXT: [[INDUCTION:%.*]] = add <2 x i32> [[BROADCAST_SPLAT]], <i32 0, i32 2> |
| ; CHECK-NEXT: br label [[VEC_EPILOG_VECTOR_BODY:%.*]] |
| ; CHECK: vec.epilog.vector.body: |
| ; CHECK-NEXT: [[INDEX23:%.*]] = phi i64 [ [[VEC_EPILOG_RESUME_VAL]], [[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT26:%.*]], [[VEC_EPILOG_VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[VEC_IND24:%.*]] = phi <2 x i32> [ [[INDUCTION]], [[VEC_EPILOG_PH]] ], [ [[VEC_IND_NEXT27:%.*]], [[VEC_EPILOG_VECTOR_BODY]] ] |
| ; CHECK-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX23]], 2 |
| ; CHECK-NEXT: [[TMP87:%.*]] = getelementptr double, ptr [[SRC]], i64 [[OFFSET_IDX]] |
| ; CHECK-NEXT: [[TMP88:%.*]] = getelementptr i8, ptr [[TMP87]], i64 -8 |
| ; CHECK-NEXT: [[TMP89:%.*]] = sub nsw <2 x i32> zeroinitializer, [[VEC_IND24]] |
| ; CHECK-NEXT: [[TMP90:%.*]] = sext <2 x i32> [[TMP89]] to <2 x i64> |
| ; CHECK-NEXT: [[TMP91:%.*]] = extractelement <2 x i64> [[TMP90]], i32 0 |
| ; CHECK-NEXT: [[TMP92:%.*]] = extractelement <2 x i64> [[TMP90]], i32 1 |
| ; CHECK-NEXT: [[TMP93:%.*]] = getelementptr double, ptr [[BASE]], i64 [[TMP91]] |
| ; CHECK-NEXT: [[TMP94:%.*]] = getelementptr double, ptr [[BASE]], i64 [[TMP92]] |
| ; CHECK-NEXT: [[TMP95:%.*]] = load double, ptr [[TMP93]], align 8, !alias.scope [[META17]] |
| ; CHECK-NEXT: [[TMP96:%.*]] = load double, ptr [[TMP94]], align 8, !alias.scope [[META17]] |
| ; CHECK-NEXT: [[TMP97:%.*]] = insertelement <2 x double> poison, double [[TMP95]], i32 0 |
| ; CHECK-NEXT: [[TMP98:%.*]] = insertelement <2 x double> [[TMP97]], double [[TMP96]], i32 1 |
| ; CHECK-NEXT: [[TMP99:%.*]] = shufflevector <2 x double> zeroinitializer, <2 x double> [[TMP98]], <4 x i32> <i32 0, i32 1, i32 2, i32 3> |
| ; CHECK-NEXT: [[INTERLEAVED_VEC25:%.*]] = shufflevector <4 x double> [[TMP99]], <4 x double> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3> |
| ; CHECK-NEXT: store <4 x double> [[INTERLEAVED_VEC25]], ptr [[TMP88]], align 8, !alias.scope [[META20]], !noalias [[META17]] |
| ; CHECK-NEXT: [[INDEX_NEXT26]] = add nuw i64 [[INDEX23]], 2 |
| ; CHECK-NEXT: [[VEC_IND_NEXT27]] = add <2 x i32> [[VEC_IND24]], splat (i32 4) |
| ; CHECK-NEXT: [[TMP100:%.*]] = icmp eq i64 [[INDEX_NEXT26]], [[N_VEC21]] |
| ; CHECK-NEXT: br i1 [[TMP100]], label [[VEC_EPILOG_MIDDLE_BLOCK:%.*]], label [[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP24:![0-9]+]] |
| ; CHECK: vec.epilog.middle.block: |
| ; CHECK-NEXT: [[CMP_N28:%.*]] = icmp eq i64 [[TMP1]], [[N_VEC21]] |
| ; CHECK-NEXT: br i1 [[CMP_N28]], label [[EXIT]], label [[VEC_EPILOG_SCALAR_PH]] |
| ; CHECK: vec.epilog.scalar.ph: |
| ; CHECK-NEXT: [[BC_RESUME_VAL29:%.*]] = phi i64 [ [[TMP84]], [[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[IND_END]], [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[VECTOR_MEMCHECK]] ], [ 0, [[VECTOR_SCEVCHECK]] ], [ 0, [[ITER_CHECK:%.*]] ] |
| ; CHECK-NEXT: [[BC_RESUME_VAL30:%.*]] = phi i64 [ [[TMP85]], [[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[IND_END32]], [[VEC_EPILOG_ITER_CHECK]] ], [ [[N]], [[VECTOR_MEMCHECK]] ], [ [[N]], [[VECTOR_SCEVCHECK]] ], [ [[N]], [[ITER_CHECK]] ] |
| ; CHECK-NEXT: [[BC_RESUME_VAL31:%.*]] = phi i32 [ [[TMP86]], [[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[IND_END34]], [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[VECTOR_MEMCHECK]] ], [ 0, [[VECTOR_SCEVCHECK]] ], [ 0, [[ITER_CHECK]] ] |
| ; CHECK-NEXT: br label [[LOOP:%.*]] |
| ; CHECK: loop: |
| ; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL29]], [[VEC_EPILOG_SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ] |
| ; CHECK-NEXT: [[COUNT:%.*]] = phi i64 [ [[BC_RESUME_VAL30]], [[VEC_EPILOG_SCALAR_PH]] ], [ [[COUNT_NEXT:%.*]], [[LOOP]] ] |
| ; CHECK-NEXT: [[IV_I32:%.*]] = phi i32 [ [[BC_RESUME_VAL31]], [[VEC_EPILOG_SCALAR_PH]] ], [ [[IV_I32_NEXT:%.*]], [[LOOP]] ] |
| ; CHECK-NEXT: [[GEP_1:%.*]] = getelementptr double, ptr [[SRC]], i64 [[IV]] |
| ; CHECK-NEXT: [[GEP_2:%.*]] = getelementptr i8, ptr [[GEP_1]], i64 -8 |
| ; CHECK-NEXT: store double 0.000000e+00, ptr [[GEP_2]], align 8 |
| ; CHECK-NEXT: [[NEG:%.*]] = sub nsw i32 0, [[IV_I32]] |
| ; CHECK-NEXT: [[NEG_EXT:%.*]] = sext i32 [[NEG]] to i64 |
| ; CHECK-NEXT: [[GEP_3:%.*]] = getelementptr double, ptr [[BASE]], i64 [[NEG_EXT]] |
| ; CHECK-NEXT: [[L:%.*]] = load double, ptr [[GEP_3]], align 8 |
| ; CHECK-NEXT: store double [[L]], ptr [[GEP_1]], align 8 |
| ; CHECK-NEXT: [[IV_I32_NEXT]] = add i32 [[IV_I32]], 2 |
| ; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 2 |
| ; CHECK-NEXT: [[COUNT_NEXT]] = add i64 [[COUNT]], -1 |
| ; CHECK-NEXT: [[EC:%.*]] = icmp sgt i64 [[COUNT]], 0 |
| ; CHECK-NEXT: br i1 [[EC]], label [[LOOP]], label [[EXIT]], !llvm.loop [[LOOP25:![0-9]+]] |
| ; CHECK: exit: |
| ; CHECK-NEXT: ret void |
| ; |
| entry: |
| br label %loop |
| |
| loop: |
| %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] |
| %count = phi i64 [ %n, %entry ], [ %count.next, %loop ] |
| %iv.i32 = phi i32 [ 0, %entry ], [ %iv.i32.next, %loop ] |
| %gep.1 = getelementptr double, ptr %src, i64 %iv |
| %gep.2 = getelementptr i8, ptr %gep.1, i64 -8 |
| store double 0.000000e+00, ptr %gep.2, align 8 |
| %neg = sub nsw i32 0, %iv.i32 |
| %neg.ext = sext i32 %neg to i64 |
| %gep.3 = getelementptr double, ptr %base, i64 %neg.ext |
| %l = load double, ptr %gep.3, align 8 |
| store double %l, ptr %gep.1, align 8 |
| %iv.i32.next = add i32 %iv.i32, 2 |
| %iv.next = add i64 %iv, 2 |
| %count.next = add i64 %count, -1 |
| %ec = icmp sgt i64 %count, 0 |
| br i1 %ec, label %loop, label %exit |
| |
| exit: |
| ret void |
| } |
| |
| attributes #0 = { "target-cpu"="neoverse-v2" } |
| |
| ;. |
| ; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]} |
| ; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1} |
| ; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"} |
| ; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]} |
| ; CHECK: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]} |
| ; CHECK: [[LOOP5]] = distinct !{[[LOOP5]], [[META2]], [[META1]]} |
| ; CHECK: [[LOOP6]] = distinct !{[[LOOP6]], [[META1]], [[META2]]} |
| ; CHECK: [[LOOP7]] = distinct !{[[LOOP7]], [[META1]], [[META2]]} |
| ; CHECK: [[PROF8]] = !{!"branch_weights", i32 8, i32 8} |
| ; CHECK: [[LOOP9]] = distinct !{[[LOOP9]], [[META1]], [[META2]]} |
| ; CHECK: [[LOOP10]] = distinct !{[[LOOP10]], [[META2]], [[META1]]} |
| ; CHECK: [[LOOP11]] = distinct !{[[LOOP11]], [[META1]], [[META2]]} |
| ; CHECK: [[LOOP12]] = distinct !{[[LOOP12]], [[META2]], [[META1]]} |
| ; CHECK: [[LOOP13]] = distinct !{[[LOOP13]], [[META1]], [[META2]]} |
| ; CHECK: [[LOOP14]] = distinct !{[[LOOP14]], [[META1]]} |
| ; CHECK: [[LOOP15]] = distinct !{[[LOOP15]], [[META1]], [[META2]]} |
| ; CHECK: [[LOOP16]] = distinct !{[[LOOP16]], [[META1]]} |
| ; CHECK: [[META17]] = !{[[META18:![0-9]+]]} |
| ; CHECK: [[META18]] = distinct !{[[META18]], [[META19:![0-9]+]]} |
| ; CHECK: [[META19]] = distinct !{[[META19]], !"LVerDomain"} |
| ; CHECK: [[META20]] = !{[[META21:![0-9]+]]} |
| ; CHECK: [[META21]] = distinct !{[[META21]], [[META19]]} |
| ; CHECK: [[LOOP22]] = distinct !{[[LOOP22]], [[META1]], [[META2]]} |
| ; CHECK: [[PROF23]] = !{!"branch_weights", i32 2, i32 6} |
| ; CHECK: [[LOOP24]] = distinct !{[[LOOP24]], [[META1]], [[META2]]} |
| ; CHECK: [[LOOP25]] = distinct !{[[LOOP25]], [[META1]]} |
| ;. |
