)]}'
{
  "commit": "4f9391aedc5a9088645f906130894bfd21552026",
  "tree": "79f72505e96e032dba7017e63e9568d25f195204",
  "parents": [
    "9c963eecaaa5e9ef270e235a8b35f05e33b597ed",
    "591d5dab2b8b52dba46907ac2d630eb1a184d75e"
  ],
  "author": {
    "name": "Rust timing bot",
    "email": "rust-timer@users.noreply.github.com",
    "time": "Thu Jun 04 01:17:17 2026 +0200"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Thu Jun 04 01:17:17 2026 +0200"
  },
  "message": "Unrolled build for #157085\nRollup merge of #157085 - RalfJung:powerpc-abi-features, r\u003dpetrochenkov\n\npowerpc: warn against incorrect values for ABI-relevant target features\n\nThis fills in https://github.com/rust-lang/rust/issues/131799 for PowerPC. Based on [this comment](https://github.com/rust-lang/rust/issues/131799#issuecomment-2731206417) by @beetrees, the relevant target features are \"hard-float\" and \"spe\". I confirmed this by looking at the LLVM sources:\n```\n  // Set up the register classes.\n  addRegisterClass(MVT::i32, \u0026PPC::GPRCRegClass);\n  if (!useSoftFloat()) {\n    if (hasSPE()) {\n      addRegisterClass(MVT::f32, \u0026PPC::GPRCRegClass);\n      // EFPU2 APU only supports f32\n      if (!Subtarget.hasEFPU2())\n        addRegisterClass(MVT::f64, \u0026PPC::SPERCRegClass);\n    } else {\n      addRegisterClass(MVT::f32, \u0026PPC::F4RCRegClass);\n      addRegisterClass(MVT::f64, \u0026PPC::F8RCRegClass);\n    }\n  }\n```\n(this is in `llvm/lib/Target/PowerPC/PPCISelLowering.cpp`)\n\nSo, we make rustc emit a warning indicating the ABI compatibility issues if \"spe\" or hard-float\" gets toggled. The plan is to eventually make this a hard error.\n\nI also found this code there, in the handling for \"altivec\", that look like they are enabling more registers to be used for the ABI, but maybe I am missing a subtle difference in these `addRegisterClass` calls:\n```\n      if (Subtarget.hasP8Vector())\n        addRegisterClass(MVT::f32, \u0026PPC::VSSRCRegClass);\n\n      addRegisterClass(MVT::f64, \u0026PPC::VSFRCRegClass);\n\n      addRegisterClass(MVT::v4i32, \u0026PPC::VSRCRegClass);\n      addRegisterClass(MVT::v4f32, \u0026PPC::VSRCRegClass);\n      addRegisterClass(MVT::v2f64, \u0026PPC::VSRCRegClass);\n```\nCc @nikic for help with interpreting this LLVM code.\n\nCc @Gelbpunkt @famfo @neuschaefer as maintainers of affected targets\n",
  "tree_diff": []
}