)]}'
{
  "commit": "d2ade4e2440f87b03882074c9aebe75da9840f4c",
  "tree": "219bd1d8c71b9e1ea8a1fdcaab22871b9393ce82",
  "parents": [
    "5f0d88ffcf4c97c062746e2c4dc4e68d5eab9cbc",
    "d96167fc9a3e8e412b9933f423ab993336e7ee85"
  ],
  "author": {
    "name": "Matthias Krüger",
    "email": "476013+matthiaskrgr@users.noreply.github.com",
    "time": "Wed Oct 15 07:09:54 2025 +0200"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Wed Oct 15 07:09:54 2025 +0200"
  },
  "message": "Rollup merge of #146949 - pmur:murp/improve-ppc-inline-asm, r\u003dAmanieu\n\nAdd vsx register support for ppc inline asm, and implement preserves_flag option\n\nThis should address the last(?) missing pieces of inline asm for ppc:\n\n* Explicit VSX register support. ISA 2.06 (POWER7) added a 64x128b register overlay extending the fpr\u0027s to 128b, and unifies them with the vmx (altivec) registers. Implementations details within gcc/llvm percolate up, and require using the `x` template modifier. I have updated the inline asm to implicitly include this for vsx arguments which do not specify it. ~~Support for the gcc codegen backend is still a todo.~~\n\n* Implement the `preserves_flags` option. All ABI\u0027s, and all ISAs store their flags in `cr`, and the carry bit lives inside `xer`. The other status registers hold sticky bits or control bits which do not affect branch instructions.\n\nThere is some interest in the e500 (powerpcspe) port. Architecturally, it has a very different FP ISA, and includes a simd extension called SPR (which is not IBM\u0027s cell SPE). Notably, it does not have altivec/fpr/vsx registers. It also has an SPE accumulator register which its ABI marks as volatile, but I am not sure if the compiler uses it.\n",
  "tree_diff": []
}