)]}'
{
  "commit": "2f5a71d441a268c87883bd6edaeb95df6d4e69a3",
  "tree": "0e5f1411dac51509aff9acbefea134317983de4f",
  "parents": [
    "f5c700e81a616fc3071075fe2e249096f08f71c8"
  ],
  "author": {
    "name": "Augie Fackler",
    "email": "augie@google.com",
    "time": "Wed Jul 22 08:08:40 2026 +0000"
  },
  "committer": {
    "name": "Augie Fackler",
    "email": "augie@google.com",
    "time": "Wed Jul 22 08:08:40 2026 +0000"
  },
  "message": "LLVM 24 updates (in llvm/llvm-project@bff9c544bd87) the diagnostic string for the RISC-V GPR register class in MC. As a result, invalid register operand references (such as x16..\u003dx31 on riscv32e targets) now emit \"register must be a GPR\" instead of \"invalid operand for instruction\".\r\n\r\nTo keep the test passing on both LLVM \u003c\u003d23 and LLVM \u003e\u003d24, split the target revisions into versioned pairs (e.g. riscv32e_llvm23 and riscv32e_llvm24) gated by `max-llvm-major-version: 23` and `min-llvm-version: 24`, respectively, with corresponding stderr references. This is admittedly a bit aggressive - I\u0027m also fine if we want to just set a max-llvm-major-version and ignore it or preemptively bump it for 24 and set the min version instead of this complexity.",
  "tree_diff": [
    {
      "type": "rename",
      "old_id": "4ae29b78b54aa910fbb01eb51cfd52ca83dfabff",
      "old_mode": 33188,
      "old_path": "tests/ui/asm/riscv/riscv32e-registers.riscv32e.stderr",
      "new_id": "7a6bf6e5176d02a54d7bc4fed151e52346fefed1",
      "new_mode": 33188,
      "new_path": "tests/ui/asm/riscv/riscv32e-registers.riscv32e_llvm23.stderr",
      "score": 86
    },
    {
      "type": "copy",
      "old_id": "4ae29b78b54aa910fbb01eb51cfd52ca83dfabff",
      "old_mode": 33188,
      "old_path": "tests/ui/asm/riscv/riscv32e-registers.riscv32e.stderr",
      "new_id": "94625fabf675029fd73162c80cb8bcbb059b8b51",
      "new_mode": 33188,
      "new_path": "tests/ui/asm/riscv/riscv32e-registers.riscv32e_llvm24.stderr",
      "score": 70
    },
    {
      "type": "delete",
      "old_id": "4ae29b78b54aa910fbb01eb51cfd52ca83dfabff",
      "old_mode": 33188,
      "old_path": "tests/ui/asm/riscv/riscv32e-registers.riscv32em.stderr",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "copy",
      "old_id": "4ae29b78b54aa910fbb01eb51cfd52ca83dfabff",
      "old_mode": 33188,
      "old_path": "tests/ui/asm/riscv/riscv32e-registers.riscv32e.stderr",
      "new_id": "7a6bf6e5176d02a54d7bc4fed151e52346fefed1",
      "new_mode": 33188,
      "new_path": "tests/ui/asm/riscv/riscv32e-registers.riscv32em_llvm23.stderr",
      "score": 86
    },
    {
      "type": "copy",
      "old_id": "4ae29b78b54aa910fbb01eb51cfd52ca83dfabff",
      "old_mode": 33188,
      "old_path": "tests/ui/asm/riscv/riscv32e-registers.riscv32e.stderr",
      "new_id": "94625fabf675029fd73162c80cb8bcbb059b8b51",
      "new_mode": 33188,
      "new_path": "tests/ui/asm/riscv/riscv32e-registers.riscv32em_llvm24.stderr",
      "score": 70
    },
    {
      "type": "delete",
      "old_id": "4ae29b78b54aa910fbb01eb51cfd52ca83dfabff",
      "old_mode": 33188,
      "old_path": "tests/ui/asm/riscv/riscv32e-registers.riscv32emc.stderr",
      "new_id": "0000000000000000000000000000000000000000",
      "new_mode": 0,
      "new_path": "/dev/null"
    },
    {
      "type": "copy",
      "old_id": "4ae29b78b54aa910fbb01eb51cfd52ca83dfabff",
      "old_mode": 33188,
      "old_path": "tests/ui/asm/riscv/riscv32e-registers.riscv32e.stderr",
      "new_id": "7a6bf6e5176d02a54d7bc4fed151e52346fefed1",
      "new_mode": 33188,
      "new_path": "tests/ui/asm/riscv/riscv32e-registers.riscv32emc_llvm23.stderr",
      "score": 86
    },
    {
      "type": "copy",
      "old_id": "4ae29b78b54aa910fbb01eb51cfd52ca83dfabff",
      "old_mode": 33188,
      "old_path": "tests/ui/asm/riscv/riscv32e-registers.riscv32e.stderr",
      "new_id": "94625fabf675029fd73162c80cb8bcbb059b8b51",
      "new_mode": 33188,
      "new_path": "tests/ui/asm/riscv/riscv32e-registers.riscv32emc_llvm24.stderr",
      "score": 70
    },
    {
      "type": "modify",
      "old_id": "70231edddbc62a690cfbf7f43460b38bf148a7f0",
      "old_mode": 33188,
      "old_path": "tests/ui/asm/riscv/riscv32e-registers.rs",
      "new_id": "a5f4151b2c80a40169388c98b985cc4644dc74aa",
      "new_mode": 33188,
      "new_path": "tests/ui/asm/riscv/riscv32e-registers.rs"
    }
  ]
}