; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefixes=CHECK-LE-P8
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
; RUN:   -mcpu=pwr9 < %s | FileCheck %s --check-prefixes=CHECK-P9
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
; RUN:   -mcpu=pwr8 < %s | FileCheck %s --check-prefixes=CHECK-BE-P8

define <16 x i8> @test_vpermxorb() local_unnamed_addr {
; CHECK-LE-P8-LABEL: test_vpermxorb:
; CHECK-LE-P8:       # %bb.0: # %entry
; CHECK-LE-P8-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
; CHECK-LE-P8-NEXT:    addis 4, 2, .LCPI0_1@toc@ha
; CHECK-LE-P8-NEXT:    addi 3, 3, .LCPI0_0@toc@l
; CHECK-LE-P8-NEXT:    lvx 2, 0, 3
; CHECK-LE-P8-NEXT:    addi 3, 4, .LCPI0_1@toc@l
; CHECK-LE-P8-NEXT:    lvx 3, 0, 3
; CHECK-LE-P8-NEXT:    vpermxor 2, 3, 2, 2
; CHECK-LE-P8-NEXT:    blr
;
; CHECK-P9-LABEL: test_vpermxorb:
; CHECK-P9:       # %bb.0: # %entry
; CHECK-P9-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
; CHECK-P9-NEXT:    addi 3, 3, .LCPI0_0@toc@l
; CHECK-P9-NEXT:    lxv 34, 0(3)
; CHECK-P9-NEXT:    addis 3, 2, .LCPI0_1@toc@ha
; CHECK-P9-NEXT:    addi 3, 3, .LCPI0_1@toc@l
; CHECK-P9-NEXT:    lxv 35, 0(3)
; CHECK-P9-NEXT:    vpermxor 2, 3, 2, 2
; CHECK-P9-NEXT:    blr
;
; CHECK-BE-P8-LABEL: test_vpermxorb:
; CHECK-BE-P8:       # %bb.0: # %entry
; CHECK-BE-P8-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
; CHECK-BE-P8-NEXT:    addis 4, 2, .LCPI0_1@toc@ha
; CHECK-BE-P8-NEXT:    addi 3, 3, .LCPI0_0@toc@l
; CHECK-BE-P8-NEXT:    addi 4, 4, .LCPI0_1@toc@l
; CHECK-BE-P8-NEXT:    lxvw4x 34, 0, 3
; CHECK-BE-P8-NEXT:    lxvw4x 35, 0, 4
; CHECK-BE-P8-NEXT:    vpermxor 2, 3, 2, 2
; CHECK-BE-P8-NEXT:    blr
entry:
  %0 = tail call <16 x i8> @llvm.ppc.altivec.crypto.vpermxor.be(<16 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16>, <16 x i8> <i8 113, i8 114, i8 115, i8 116, i8 117, i8 118, i8 119, i8 120, i8 121, i8 122, i8 123, i8 124, i8 125, i8 126, i8 127, i8 112>, <16 x i8> <i8 113, i8 114, i8 115, i8 116, i8 117, i8 118, i8 119, i8 120, i8 121, i8 122, i8 123, i8 124, i8 125, i8 126, i8 127, i8 112>)
  ret <16 x i8> %0
}

declare <16 x i8> @llvm.ppc.altivec.crypto.vpermxor.be(<16 x i8>, <16 x i8>, <16 x i8>)

define <8 x i16> @test_vpermxorh() local_unnamed_addr {
; CHECK-LE-P8-LABEL: test_vpermxorh:
; CHECK-LE-P8:       # %bb.0: # %entry
; CHECK-LE-P8-NEXT:    addis 3, 2, .LCPI1_0@toc@ha
; CHECK-LE-P8-NEXT:    addis 4, 2, .LCPI1_1@toc@ha
; CHECK-LE-P8-NEXT:    addi 3, 3, .LCPI1_0@toc@l
; CHECK-LE-P8-NEXT:    lvx 2, 0, 3
; CHECK-LE-P8-NEXT:    addi 3, 4, .LCPI1_1@toc@l
; CHECK-LE-P8-NEXT:    lvx 3, 0, 3
; CHECK-LE-P8-NEXT:    vpermxor 2, 3, 2, 2
; CHECK-LE-P8-NEXT:    blr
;
; CHECK-P9-LABEL: test_vpermxorh:
; CHECK-P9:       # %bb.0: # %entry
; CHECK-P9-NEXT:    addis 3, 2, .LCPI1_0@toc@ha
; CHECK-P9-NEXT:    addi 3, 3, .LCPI1_0@toc@l
; CHECK-P9-NEXT:    lxv 34, 0(3)
; CHECK-P9-NEXT:    addis 3, 2, .LCPI1_1@toc@ha
; CHECK-P9-NEXT:    addi 3, 3, .LCPI1_1@toc@l
; CHECK-P9-NEXT:    lxv 35, 0(3)
; CHECK-P9-NEXT:    vpermxor 2, 3, 2, 2
; CHECK-P9-NEXT:    blr
;
; CHECK-BE-P8-LABEL: test_vpermxorh:
; CHECK-BE-P8:       # %bb.0: # %entry
; CHECK-BE-P8-NEXT:    addis 3, 2, .LCPI1_0@toc@ha
; CHECK-BE-P8-NEXT:    addis 4, 2, .LCPI1_1@toc@ha
; CHECK-BE-P8-NEXT:    addi 3, 3, .LCPI1_0@toc@l
; CHECK-BE-P8-NEXT:    addi 4, 4, .LCPI1_1@toc@l
; CHECK-BE-P8-NEXT:    lxvw4x 34, 0, 3
; CHECK-BE-P8-NEXT:    lxvw4x 35, 0, 4
; CHECK-BE-P8-NEXT:    vpermxor 2, 3, 2, 2
; CHECK-BE-P8-NEXT:    blr
entry:
  %0 = tail call <16 x i8> @llvm.ppc.altivec.crypto.vpermxor.be(<16 x i8> <i8 2, i8 1, i8 4, i8 3, i8 6, i8 5, i8 8, i8 7, i8 10, i8 9, i8 12, i8 11, i8 14, i8 13, i8 16, i8 15>, <16 x i8> <i8 114, i8 113, i8 116, i8 115, i8 118, i8 117, i8 120, i8 119, i8 122, i8 121, i8 124, i8 123, i8 126, i8 125, i8 112, i8 127>, <16 x i8> <i8 114, i8 113, i8 116, i8 115, i8 118, i8 117, i8 120, i8 119, i8 122, i8 121, i8 124, i8 123, i8 126, i8 125, i8 112, i8 127>)
  %1 = bitcast <16 x i8> %0 to <8 x i16>
  ret <8 x i16> %1
}

define <4 x i32> @test_vpermxorw() local_unnamed_addr {
; CHECK-LE-P8-LABEL: test_vpermxorw:
; CHECK-LE-P8:       # %bb.0: # %entry
; CHECK-LE-P8-NEXT:    addis 3, 2, .LCPI2_0@toc@ha
; CHECK-LE-P8-NEXT:    addis 4, 2, .LCPI2_1@toc@ha
; CHECK-LE-P8-NEXT:    addi 3, 3, .LCPI2_0@toc@l
; CHECK-LE-P8-NEXT:    lvx 2, 0, 3
; CHECK-LE-P8-NEXT:    addi 3, 4, .LCPI2_1@toc@l
; CHECK-LE-P8-NEXT:    lvx 3, 0, 3
; CHECK-LE-P8-NEXT:    vpermxor 2, 3, 2, 2
; CHECK-LE-P8-NEXT:    blr
;
; CHECK-P9-LABEL: test_vpermxorw:
; CHECK-P9:       # %bb.0: # %entry
; CHECK-P9-NEXT:    addis 3, 2, .LCPI2_0@toc@ha
; CHECK-P9-NEXT:    addi 3, 3, .LCPI2_0@toc@l
; CHECK-P9-NEXT:    lxv 34, 0(3)
; CHECK-P9-NEXT:    addis 3, 2, .LCPI2_1@toc@ha
; CHECK-P9-NEXT:    addi 3, 3, .LCPI2_1@toc@l
; CHECK-P9-NEXT:    lxv 35, 0(3)
; CHECK-P9-NEXT:    vpermxor 2, 3, 2, 2
; CHECK-P9-NEXT:    blr
;
; CHECK-BE-P8-LABEL: test_vpermxorw:
; CHECK-BE-P8:       # %bb.0: # %entry
; CHECK-BE-P8-NEXT:    addis 3, 2, .LCPI2_0@toc@ha
; CHECK-BE-P8-NEXT:    addis 4, 2, .LCPI2_1@toc@ha
; CHECK-BE-P8-NEXT:    addi 3, 3, .LCPI2_0@toc@l
; CHECK-BE-P8-NEXT:    addi 4, 4, .LCPI2_1@toc@l
; CHECK-BE-P8-NEXT:    lxvw4x 34, 0, 3
; CHECK-BE-P8-NEXT:    lxvw4x 35, 0, 4
; CHECK-BE-P8-NEXT:    vpermxor 2, 3, 2, 2
; CHECK-BE-P8-NEXT:    blr
entry:
  %0 = tail call <16 x i8> @llvm.ppc.altivec.crypto.vpermxor.be(<16 x i8> <i8 4, i8 3, i8 2, i8 1, i8 8, i8 7, i8 6, i8 5, i8 12, i8 11, i8 10, i8 9, i8 16, i8 15, i8 14, i8 13>, <16 x i8> <i8 116, i8 115, i8 114, i8 113, i8 120, i8 119, i8 118, i8 117, i8 124, i8 123, i8 122, i8 121, i8 112, i8 127, i8 126, i8 125>, <16 x i8> <i8 116, i8 115, i8 114, i8 113, i8 120, i8 119, i8 118, i8 117, i8 124, i8 123, i8 122, i8 121, i8 112, i8 127, i8 126, i8 125>)
  %1 = bitcast <16 x i8> %0 to <4 x i32>
  ret <4 x i32> %1
}

define <2 x i64> @test_vpermxord() local_unnamed_addr {
; CHECK-LE-P8-LABEL: test_vpermxord:
; CHECK-LE-P8:       # %bb.0: # %entry
; CHECK-LE-P8-NEXT:    addis 3, 2, .LCPI3_0@toc@ha
; CHECK-LE-P8-NEXT:    addis 4, 2, .LCPI3_1@toc@ha
; CHECK-LE-P8-NEXT:    addi 3, 3, .LCPI3_0@toc@l
; CHECK-LE-P8-NEXT:    lvx 2, 0, 3
; CHECK-LE-P8-NEXT:    addi 3, 4, .LCPI3_1@toc@l
; CHECK-LE-P8-NEXT:    lvx 3, 0, 3
; CHECK-LE-P8-NEXT:    vpermxor 2, 3, 2, 2
; CHECK-LE-P8-NEXT:    blr
;
; CHECK-P9-LABEL: test_vpermxord:
; CHECK-P9:       # %bb.0: # %entry
; CHECK-P9-NEXT:    addis 3, 2, .LCPI3_0@toc@ha
; CHECK-P9-NEXT:    addi 3, 3, .LCPI3_0@toc@l
; CHECK-P9-NEXT:    lxv 34, 0(3)
; CHECK-P9-NEXT:    addis 3, 2, .LCPI3_1@toc@ha
; CHECK-P9-NEXT:    addi 3, 3, .LCPI3_1@toc@l
; CHECK-P9-NEXT:    lxv 35, 0(3)
; CHECK-P9-NEXT:    vpermxor 2, 3, 2, 2
; CHECK-P9-NEXT:    blr
;
; CHECK-BE-P8-LABEL: test_vpermxord:
; CHECK-BE-P8:       # %bb.0: # %entry
; CHECK-BE-P8-NEXT:    addis 3, 2, .LCPI3_0@toc@ha
; CHECK-BE-P8-NEXT:    addis 4, 2, .LCPI3_1@toc@ha
; CHECK-BE-P8-NEXT:    addi 3, 3, .LCPI3_0@toc@l
; CHECK-BE-P8-NEXT:    addi 4, 4, .LCPI3_1@toc@l
; CHECK-BE-P8-NEXT:    lxvw4x 34, 0, 3
; CHECK-BE-P8-NEXT:    lxvw4x 35, 0, 4
; CHECK-BE-P8-NEXT:    vpermxor 2, 3, 2, 2
; CHECK-BE-P8-NEXT:    blr
entry:
  %0 = tail call <16 x i8> @llvm.ppc.altivec.crypto.vpermxor.be(<16 x i8> <i8 8, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 16, i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9>, <16 x i8> <i8 120, i8 119, i8 118, i8 117, i8 116, i8 115, i8 114, i8 113, i8 112, i8 127, i8 126, i8 125, i8 124, i8 123, i8 122, i8 121>, <16 x i8> <i8 120, i8 119, i8 118, i8 117, i8 116, i8 115, i8 114, i8 113, i8 112, i8 127, i8 126, i8 125, i8 124, i8 123, i8 122, i8 121>)
  %1 = bitcast <16 x i8> %0 to <2 x i64>
  ret <2 x i64> %1
}