)]}'
{
  "id": "3091fe85fa8bccc6ba1cc6738005aa9cbef7d4f7",
  "repo": "llvm-project",
  "revision": "refs/heads/rust-revert-fastisel",
  "path": "llvm/test/CodeGen/AMDGPU/sreg-xnull-regclass-bitwidth.mir"
}